NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
130 Freescale Semiconductor, Inc.
13.19 EPR Register - EPR (RPAGE = 1)
The EPR register contains eight control bits for the RFM as described in Figure 109 . The function of the upper 4 bits depends on
the state of the VCD_EN bit.
$0038 Bit 7 6 5 4 3 2 1 Bit 0
R
PLL_LPF_[2:0] PA_SLOPE VCD_EN
W
RFMRST:
0 0 1 1 0 0 1 0
= Reserved
Figure 109. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 0)
$0038 Bit 7 6 5 4 3 2 1 Bit 0
R
VCD[3:0]
PA_SLOPE VCD_EN
W
RFMRST:
— — — — 0 0 1 0
= Reserved
Figure 110. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 1)
Table 84. EPR Field Descriptions
Field Description
7
Reserved
Reserved bit — Not for user access if the VCD_EN bit is clear.
6-4
PLL_LPF_[2:0]
Low Pass Filter Selection - These read/write bits select the PLL low pass filter. A reset sets these bits to $03. These bits
are only accessible if the VCD_EN bit is clear.
7-4
VCD[3:0]
VCO Calibration Count Difference - These read-only bits show the count difference from “ideal” when the VCO calibration
machine is finished (see Section 13.21 ). These bits are only accessible when the VCD_EN bit is set. Writing to these bits
when the VCD_EN bit is set has no effect. The reset state is undefined.
3-2
Reserved
Reserved bits — Not for user access.
1
PA_SLOPE
PA Output Slope Selection — This read/write bit controls the output slope of the RFM PA output. This bit is set by the
RFMRST signal.
0
VCD_EN
VCD Enable bit — This bit allows access to the VCD[3:0] bits. This bit is cleared by the RFMRST signal.
0 PLL_LPF_[2:0] bits accessed.
1 VCD[3:0] bits accessed.