NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
102 Freescale Semiconductor, Inc.
Figure 77. LF Detector Sampling Timing
12.17.3 LF Control Register 3 (LFCTL3)
LFCTL3 contains the control bits for the LF sampling interval and the minimum required carrier detection time when using the
carrier detect mode.
$0022 Bit 7 6 5 4 3 2 1 Bit 0
R
LFDO
TOGMOD SYNC[1:0] LFCDTM[3:0]
W
Reset:
— 0 0 1 0 0 0 0
= Reserved
Figure 78. LFR Control Register 3 (LFCTL3)
Table 61. LFCTL3 Register Field Descriptions
Field Description
7
LFDO
LF Detector Output — This read-only bit follows the bit slicer output signal that goes high during the presence of a carrier. It
may change at any time. This bit is read only and unaffected by any reset.
0
LF detector output low (no signal above threshold)
1 LF detector output high (received signal above threshold)
6
TOGMOD
LFR Mode Toggle — This read/write bit enables the toggling of the CARMOD bit at each new LFON sequence. Reset clears
this bit.
0
CARMOD bit does not change and determines detector mode.
1 CARMOD bit will be toggled every LFON detection sequence, starting by CARMOD selection.
Therefore the reception chain will alternately look for a carrier frame or for a data frame.
5:4
SYNC[1:0]
LF SYNC Selection — Selects the type of SYNC pattern as described in Figure 73 . Reset presets these bits to the 01 (6T SYNC)
option. Compatible with preamble consisting of minimum 2 ms Manchester data to allow for proper averaging filter operation.
00
For factory test purposes, not intended for use in any application.
01 6T SYNC pattern
10 7.5T SYNC pattern
11 9T SYNC pattern
LFR Detector Active
LFONTM
LFSTM
Power Up
Settling Time Power Up
Settling Time
LFONTM
time segments not to scale
t
DEC
LF searching for
SYNC pattern