NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
104 Freescale Semiconductor, Inc.
12.17.4 LFR Control Register 4 (LFCTL4)
LFCTL4 contains local interrupt enable control bits. The provided I-interrupts are not globally masked by the I bit in the CPU’s
CCR, setting one or more of these interrupt enable control bits will cause a CPU interrupt to be requested whenever the flag bit
associated with the corresponding LFR interrupt source becomes set. It is good practice to clear any flag bits in the LFS register
before setting interrupt enable bits in this register in order to avoid an immediate interrupt request.
$0023 Bit 7 6 5 4 3 2 1 Bit 0
R
LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT[1:0]
W
Reset:
0 0 0 0 1 1 0 0
Figure 79. LFR Control Register 4 (LFCTL4)
Table 62. LFCTL4 Register Field Descriptions
Field Description
7
LFDRIE
LFR Data Register Full Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR data register
is full. Reset clears LFDRIE.
0
LFDRF interrupts disabled. Use software polling.
1 LFR Data Register Full interrupts are enabled. If LFDRIE is set,
then an interrupt is requested when LFDRF = 1.
6
LFERIE
LFR Error Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects an error in reception
of a non-Manchester encoded bit time following the SYNC time. Reset clears LFERIE.
0
LFERF interrupts disabled. Use software polling.
1 LFERF interrupts are enabled. If LFERIE is set, then an interrupt is requested when LFERF = 1.
5
LFCDIE
LFR Carrier Detect Interrupt Enable — This read/write bit enables the LFCDF interrupt when the LFR detects the number of
samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register. The LFCDIE is ignored when the LFR is operating
in the data mode (CARMOD = 0), except when DECEN is cleared. Reset clears LFCDIE.
0
LFCDF interrupts disabled.
1 LFR LFCDF interrupts are enabled. If LFCDIE is set, then an interrupt is requested when LFCDF = 1.
4
LFIDIE
LFR ID Detect Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects a match to the
ID code selected in the LFIDH:L registers. Reset clears LFIDIE.
0
LFIDF interrupts disabled.
1 LFIDF interrupts are enabled. If LFIDIE is set, then an interrupt is requested when LFIDF = 1.
3
DECEN
LF Digital Decode Enable — This read/write bit enables the data processing by the digital decoder. When
disabled, the frame format (Manchester, data-rate, SYNC, data) is not checked. There is no more error flag assertion (data, error,
ID). The MCU should then poll the LFDO bit to extract from the analog detector the bit stream. Reset sets the DECEN bit.
0
Digital decoder is disabled.
1 Digital decoder is enabled.
2
VALEN
LF Validation Enable — This read/write bit enables the carrier validation process. Reset sets this bit.
0 Carrier Validation disabled.
1 Carrier Validation enabled.
1:0
TIMOUT
[1:0]
SYNC Time Out Select — These two read/write bits select the period of time that the LFR will search for a SYNC pattern in the
data mode. If the SYNC pattern is not detected the LFR will be turned off after this delay time. These time intervals are clocked
by the internal LFRO clock. Reset clears TIMOUT bit.
00
SYNC word is continuously searched — no timeout.
01 SYNC search time set to nominal 8 milliseconds.
10 SYNC search time set to nominal 24 milliseconds.
11 SYNC search time set to nominal 48 milliseconds.