NXP Semiconductors FXTH870 D Series, Manual

Page: 49 / 176

FXTH870xD
Sensors
Freescale Semiconductor, Inc.
47
Table 33. Port A Data Register Field Descriptions
Field Description
4:0
PTAD
[4:0]
Port A Data Register Bit — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the
corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins
as high-impedance inputs with pullups disabled.
$0001 Bit 7 6 5 4 3 2 1 Bit 0
R
PTAPE[3:0]
W
Reset:
0 0 0 0 0 0 0 0
= Reserved
Figure 31. Internal Pullup Enable for Port A Register (PTAPE)
Table 34. Port A Register Pullup Enable Field Descriptions
Field Description
3:0
PTAPE
[3:0]
Internal Pullup Enable for Port A Bit n — Each of these control bits determines if the internal pullup device is enabled for the
associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are
disabled.
0
Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
$0003 Bit 7 6 5 4 3 2 1 Bit 0
R
PTADD[3:0]
W
Reset:
0 0 0 0 0 0 0 0
= Reserved
Figure 32. Data Direction for Port A Register (PTADD)
Table 35. Port A Data Direction Field Descriptions
Field Description
3:0
PTADD
[3:0]
Data Direction for Port A Bit n — These read/write bits control the direction of port A pins and what is read for PTADD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTADD reads return the contents of PTADDn. PTA4 is input-only, therefore bit 4 will
always be 0.