NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
16 Freescale Semiconductor, Inc.
4.3 MCU Register Addresses and Bit Assignments
The registers in the FXTH870xD are divided into these four groups:
• Direct-page registers are located in the first 80 locations in the memory map; these are accessible with efficient direct
addressing mode instructions.
• The parameter registers begin at address $0050; these are also accessible with efficient direct addressing mode
instructions.
• High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room in the
direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register
locations include:
— Three values that are loaded into working registers at reset
— An 8-byte back door comparison key that optionally allows the user to gain controlled access to secure memory.
Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory
locations.
Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct
addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to
access any bit in any direct-page register.
Table 3 is a summary of all user-accessible direct-page registers and control bits.
Those related to the TPMS application and modules are described in detail in this specification.
The register names in column two of the following tables are shown in bold to set them apart from the bit names to the right. Cells
that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded
cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
$DFEE:DFEF Vsm SMI
$DFF0:DFF1 Vtpm1ovf TPM1
$DFF2:DFF3 Vtpm1ch1 TPM1
$DFF4:DFF5 Vtpm1ch0 TPM1
$DFF6:DFF7 Vwuktmr PWU
$DFF8:DFF9 Vlvd Sys Ctrl - LVD
$DFFA:DFFB Reserved
$DFFC:DFFD Vswi SWI opcode
$DFFE:DFFF Vreset
Sys Ctrl - POR, PRF, COP, LVD
Temp Restart, Illegal opcode or address
Table 3. MCU Direct Page Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$00 00 PTAD PTAD[4:0]
$00 01 PTAPE PTAPE[3:0]
$00 02 Reserved
$00 03 PTADD PTADD[3:0]
$00 04 PTBD PTBD[1:0]
$00 05 PTBPE PTBPE[1:0]
$00 06 Reserved
$00 07 PTBDD PTBDD[1:0]
$00 08 Reserved
$00 09 Reserved
$00 0A Reserved
$00 0B Reserved
$00 0C KBISC 0 0 0 0 KBF KBACK KBIE KBIMOD
Table 2. Vector Summary (continued)
User Vector Addr Vector Name Module Source