NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
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8.4 Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers,
and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any
memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access
I/O and control registers or nonvolatile program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the
source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ,
and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to
specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing
mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
8.4.1 Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does
not need to access memory to get any operands.
8.4.2 Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located
in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is
sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to
continue at the branch destination address.
8.4.3 Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately
following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next
memory location after the opcode, and the low-order byte is located in the next memory location after that.
8.4.4 Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000–0x00FF).
During execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct
address from the instruction to get the 16-bit address where the desired operand is located. This is faster and more memory
efficient than specifying a complete 16-bit address for the operand.
8.4.5 Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the
opcode (high byte first).
8.4.6 Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack
pointer as the base reference.
8.4.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed
to complete the instruction.
8.4.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed
to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched.
This addressing mode is only used for MOV and CBEQ instructions.
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate
— also clear or set the carry/borrow flag.
0
No carry out of bit 7
1 Carry out of bit 7
Table 43. CCR Register Field Descriptions (continued)
Field Description