NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
54 Freescale Semiconductor, Inc.
8.3.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
During normal program execution, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an
address other than that of the next sequential location. This is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there
is the address of the first instruction that will be executed after exiting the reset state.
8.3.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of the instruction just
executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in
general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the
HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1.
Figure 41. Condition Code Register
Table 43. CCR Register Field Descriptions
Field Description
7
V
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed
branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0
No overflow
1 Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-
carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the
result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value.
0
No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when
the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are
saved on the stack, but before the first instruction of the interrupt service routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensures that the next
instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set.
0
Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces
a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the most
significant bit of the loaded or stored value was 1.
0
Non-negative result
1 Negative result
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result
of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s.
0
Non-zero result
1 Zero result
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
7 0
CCR C V 1 1 H I N Z