FXTH870xD
Sensors
146
Freescale Semiconductor, Inc.
15.3.3
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR
are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are
used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal
memory map of the MCU. Breakpoints are normally set while the target MCU is in ACTIVE BACKGROUND mode before running
the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer
to
.
15.3.4
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial BACKGROUND mode command such as WRITE_BYTE must be
used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.
Figure 119. System Background Debug Force Reset Register (SBDFR)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR
(1)
1. BDFR is writable only through serial BACKGROUND mode debug commands, not from user programs.
Reset
0
0
0
0
0
0
0
0
= Reserved
Table 92. SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset
— A serial ACTIVE BACKGROUND mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a
user program.
Summary of Contents for FXTH870 D Series
Page 86: ...FXTH870xD Sensors 84 Freescale Semiconductor Inc Figure 57 Data Flow For Measurements...
Page 171: ...FXTH870xD Sensors Freescale Semiconductor Inc 169 Figure 128 QFN Case Outline...
Page 172: ...FXTH870xD Sensors 170 Freescale Semiconductor Inc Figure 129 QFN Case Outline...
Page 173: ...FXTH870xD Sensors Freescale Semiconductor Inc 171...
