FXTH870xD
Sensors
Freescale Semiconductor, Inc.
139
15
Development Support
15.1
Introduction
This chapter describes the single-wire BACKGROUND DEBUG mode (BDM), which uses the on-chip BACKGROUND DEBUG
controller (BDC) module.
15.1.1
Features
Features of the BDC module include:
•
Single pin for mode selection and background communications
•
BDC registers are not located in the memory map
•
SYNC command to determine target communications rate
•
Non-intrusive commands for memory access
•
ACTIVE BACKGROUND mode commands for CPU register access
•
GO and TRACE1 commands
•
BACKGROUND command can wake CPU from STOP or WAIT modes
•
One hardware address breakpoint built into BDC
•
Oscillator runs in STOP mode, if BDC enabled
•
COP watchdog disabled while in ACTIVE BACKGROUND mode
15.2
Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire BACKGROUND DEBUG interface that supports in-circuit programming of
on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs,
this system does not interfere with normal application resources. It does not use any user memory or locations in the memory
map and does not share any on-chip peripherals.
BDC commands are divided into two groups:
•
ACTIVE BACKGROUND mode commands require that the target MCU is in ACTIVE BACKGROUND mode (the user
program is not running). ACTIVE BACKGROUND mode commands allow the CPU registers to be read or written, and allow
the user to trace one user instruction at a time, or GO to the user program from ACTIVE BACKGROUND mode.
•
Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands
allow a user to read or write MCU memory locations or access status and control registers within the BACKGROUND
DEBUG controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom
serial interface to the single-wire BACKGROUND DEBUG system. Depending on the development tool vendor, this interface pod
may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial
bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the
BKGD/PTA4 pin, RESET, and sometimes V
DD
. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile
memory has been programmed. Sometimes V
DD
can be used to allow the pod to use power from the target system to avoid the
need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system
without forcing a target system reset or otherwise disturbing the running application program.
Figure 114. BDM Tool Connector
2
4
6
NO CONNECT 5
NO CONNECT 3
1
RESET
BKGD
GND
V
DD
Summary of Contents for FXTH870 D Series
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