FXTH870xD
Sensors
Freescale Semiconductor, Inc.
77
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other
channels in the same TPM1 are configured for input capture or output compare functions. The period of this PWM signal is
determined by the setting in the modulus register (TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the
timer channel value register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the ELSnA
control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As
Figure 54
shows, the output compare value in the TPM1 channel registers determines the pulse width (duty cycle) of the PWM
signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow
forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow forces the
PWM signal low and the output compare forces the PWM signal high.
Figure 54. PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register
(TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the
modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit
updates and to avoid unexpected PWM pulse widths. Writes to either register, TPM1CnVH or TPM1CnVL, write to buffer
registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of
a 16-bit register have been written and the value in the 1TPMCNTH:TPM1CNTL counter is 0x0000. (The new duty cycle does
not take effect until the next full period.)
9.5.3
Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in
TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in
TPM1MODH:TPM1MODL. TPM1MODH:TPM1MODL should be kept in the range of 0x0001 to 0x7FFF because values outside
this range can produce ambiguous results. ELS0A will determine the polarity of the CPWM output.
pulse width =2 x (TPM1CnVH:TPM1CnVL)
period = 2 x (TPM1MODH:TPM1MODL);
for TPM1MODH:TPM1MODL = 0x0001–0x7FFF
If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If
TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be
100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is
0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because
the resulting period is much longer than required for normal applications.
TPM1MODH:TPM1MODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When
CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter
needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to
down-counting.
Figure 55
shows the output compare value in the TPM1 channel registers (multiplied by 2), which determines the pulse width
(duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a
compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in
TPM1MODH:TPM1MODL, then counts down until it reaches zero. This sets the period equal to two times
TPM1MODH:TPM1MODL.
PERIOD
PULSE
WIDTH
OVERFLOW
OVERFLOW
OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
TPMCH
Summary of Contents for FXTH870 D Series
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