NXP Semiconductors FXTH870 D Series, Manual

Page: 34 / 176

FXTH870xD
Sensors
32 Freescale Semiconductor, Inc.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing as intended. If the
COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SIMOPT1 register.
Even if the application will use the reset default settings in COPE, COPCLKS and COPT[2:0], the user should still write to write-
once SIMOPT1 during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application
program gets lost.
The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR
could continue to be executed periodically even if the main application program fails. When the MCU is in ACTIVE
BACKGROUND DEBUG mode, the COP timer is temporarily disabled.
5.4 SIM Test Register (SIMTST)
The output of the temperature monitor is available using the SIM Test register as shown in Figure 18 .
0 1 1 0 LFO 2
11
2048
0 1 1 1 LFO 2
11
2048
BUSCLKS[1:0]
1:1 (0.5 MHz) 1:0 (1 MHz) 0:1 (2 MHz) 0:0 (4MHz)
1 0 0 0 Bus Clock 2
13
16.384 8.192 4.096 2.048
1 0 0 1 Bus Clock 2
14
32.768 16.384 8.192 4.096
1 0 1 0 Bus Clock 2
15
65.536 32.768 16.384 8.192
1 0 1 1 Bus Clock 2
16
131.072 65.536 32.768 16.384
1 1 0 0 Bus Clock 2
17
262.144 131.072 65.536 32.768
1 1 0 1 Bus Clock 2
18
524.288 262.144 131.072 65.536
1 1 1 0 Bus Clock 2
19
1048.576 524.288 262.144 131.072
1 1 1 1 Bus Clock 2
19
1048.576 524.288 262.144 131.072
$180F Bit 7 6 5 4 3 2 1 Bit 0
R
TRH
TRO
W
RESET:
0 0 1 1 1 0 0 1
= Reserved
Figure 18. SIM Test Register (SIMTST)
Table 19. SIMTST Register Field Descriptions
Field Description
7
reserved
Reserved Bit — These bits are reserved for factory trim and should not be altered by the user.
6:4
TRH
Temperature Restart High threshold — Binary coded from 0x00 to 0x07; recommend applications overwrite to 0x06 at each
wakeup cycle.
3:1
reserved
Reserved Bit — These bits are reserved for factory trim and should not be altered by the user.
0
TRO
Temperature Restart Outside
1 TR module is outside the T
REARM
temperature range and will restart the MCU if the TRE bit is set and
temperature falls back within the T
RESET
temperature range.
0 TR module is within the T
RESET
temperature range and the MCU cannot be armed to restart when
temperature falls back to the T
RESET
range. The TRE bit cannot be set.
Table 18. COP Watchdog Timeout Period (continued)
COPCLKS
COPT
Clock
Source
COP
Overflow
Count
COP Overflow Time
(ms, nominal)
2 1 0