FXTH870xD
Sensors
76
Freescale Semiconductor, Inc.
clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock
option is one-fourth the bus rate. Refer to
and
Table 49
for more information about clock source selection.
When the microcontroller is in ACTIVE BACKGROUND mode, the TPM1 temporarily suspends all counting until the
microcontroller returns to normal user operating mode. During STOP mode, all TPM1 clocks are stopped; therefore, the TPM1
is effectively disabled until clocks resume. During WAIT mode, the TPM1 continues to operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in
up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter
counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value
in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then
counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in
TPM1MODH:TPM1MODL) are normal length counts (one timer clock period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible
indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE = 0) where no
hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically
generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-
bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the
modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the
counter changes direction at the transition from the value set in the modulus register and the next lower count value. This
corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations.
Whenever either byte of the counter is read (TPM1CNTH or TPM1CNTL), both bytes are captured into a buffer so when the other
byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count
normally, but no new value can be read from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPM1CNTH or
TPM1CNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was
read before resetting the count.
9.5.2
Channel Mode Selection
Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status
and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output
compare, and buffered edge-aligned PWM.
Input Capture Mode
With the input capture function, the TPM1 can capture the time at which an external event occurs. When an active edge occurs
on the pin of an input capture channel, the TPM1 latches the contents of the TPM1 counter into the channel value registers
(TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input
capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses
regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register
(TPM1CnSC).
An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
Output Compare Mode
With the output compare function, the TPM1 can generate timed pulses with programmable position, polarity, duration, and
frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM1 can set,
clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of
a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control
register (TPM1CnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
Summary of Contents for FXTH870 D Series
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