FXTH870xD
Sensors
70
Freescale Semiconductor, Inc.
9.4
Register Definition
The TPM1 includes:
•
An 8-bit status and control register (TPMSC)
•
A 16-bit counter (TPMCNTH:TPMCNTL)
•
A 16-bit modulo register (TPMMODH:TPMMODL)
Each timer channel has:
•
An 8-bit status and control register (TPMCnSC)
•
A 16-bit channel value register (TPMCnVH:TPMCnVL)
9.4.1
Timer Status and Control Register (TPM1SC)
TPM1SC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM1 configuration,
clock source, and prescale divisor. These controls relate to all channels within this timer module.
$0010
7
6
5
4
3
2
1
0
R
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
W
Reset
0
0
0
0
0
0
0
0
= Reserved
Figure 43. Timer Status and Control Register (TPM1SC)
Table 47. TPM1SC Register Field Descriptions
Field
Description
7
TOF
Timer Overflow Flag
— This flag is set when the TPM1 counter changes to 0x0000 after reaching the modulo value
programmed in the TPM1 counter modulo registers. When the TPM1 is configured for CPWM, TOF is set after the counter has
reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM1 status
and control register when TOF is set and then writing a 0 to TOF. If another TPM1 overflow occurs before the clearing sequence
is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset
clears TOF. Writing a 1 to TOF has no effect.
0
TPM1 counter has not reached modulo value or overflow
1
TPM1 counter has overflowed
6
TOIE
Timer Overflow Interrupt Enable
— This read/write bit enables TPM1 overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals 1. Reset clears TOIE.
0
TOF interrupts inhibited (use software polling)
1
TOF interrupts enabled
5
CPWMS
Center-Aligned PWM Select
— This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM1 operates
in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the
TPM1 to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS.
0
All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA
control bits in each channel’s status and control register
1
All TPM channels operate in center-aligned PWM mode
4:3
CLKS[B:A]
Clock Source Select
— As shown in
Table 46
, this 2-bit field is used to disable the TPM1 system or select one of three clock
sources to drive the counter prescaler. The internal DX source is synchronized to the bus clock by an on-chip synchronization
circuit.
2:0
PS[2:0]
Prescale Divisor Select
— This 3-bit field selects one of eight divisors for the TPM1 clock input as shown in
Table 48
. This
prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is
selected to drive the TPM1 system.
Summary of Contents for FXTH870 D Series
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