NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
108 Freescale Semiconductor, Inc.
NOTE
Setting CHK125[1:0] to either 0x01 or 0x10 increases the immunity to noise and therefore
carries the side effect of narrowing the 125 kHz carrier bandwidth tolerance.
12.17.9 LFR Control Register C (LFCTRLC, LPAGE = 1 )
The LFCTRLC register contains control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.
1-0
CHK125
[1:0]
Accurate 125 kHz Check — The bit controls the CARVAL frequency check method.
00 CARVAL validates on n (2*32

s packets), n depending on LFCDTM value - recommended setting for Low
Sensitivity mode.
01 CARVAL validates on n (1*32

s 4*8

s packets), n depending on LFCDTM value - optional recommended
setting for High Sensitivity mode.
10 CARVAL validates n (8*8

s packet), n depending on LFCDTM value - optional recommended
setting for High Sensitivity mode.
11 Same as 00.
$0023 Bit 7 6 5 4 3 2 1 Bit 0
R
AMPGAIN[1:0] FINSEL[1:0] AZEN LOWQ[1:0] DEQEN
W
Reset:
1 1 0 0 1 0 0 1
Figure 86. LFR Control Register C (LFCTRLC, LPAGE = 1)
Table 68. LFCTRLC Register Field Descriptions
Field Description
7-6
AMPGAIN
[1:0]
3rd Amplifier gain — These bits controls the 3rd amplifier gain.
00 Gain of 2 - recommended setting
01 Gain of 3
10 Gain of 4
11 Gain of 6
5-4
FINSEL
[1:0]
Final stage select — These bits select the final stage of the LOGAMP.
00 Continuous time biasing - Fixed Gain 6
01 Continuous time biasing - Programmable Gain - recommended setting
10 4th rectifier disabled
11 4th rectifier disabled
3
AZEN
Data AZ enable — This bit allows the AZ sequence during data frame.
0 AZ during data disabled
1 AZ during data enabled - recommended setting
2-1
LOWQ
[1:0]
DeQing Resistor — These bits select the resistor added in parallel to the input network.
00 4 k

01 2 k

10 1 k

11 500

0
DEQEN
DeQing System enable — The bit controls the DeQing system.
0 DeQing disabled.
1 DeQing enabled.
Table 67. LFCTRLD Register Field Descriptions (continued)
Field Description