NXP Semiconductors FXTH870 D Series Manual Download Page 67

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FXTH870xD

Sensors
Freescale Semiconductor, Inc.

STA

opr8a

STA

opr16a

STA

oprx16

STA

oprx8

STA ,X
STA

oprx16

,SP

STA

oprx8

,SP

Store Accumulator in
Memory



(A)

–

DIR
EXT
IX2
IX1
IX
SP2
SP1

C7
D7

9ED7

9EE7

dd
hh ll
ee ff
ff

ee ff
ff

3
4
4
3
2
5
4

STHX

opr8a

STHX

opr16a

STHX

oprx8

,SP

Store H:X (Index Reg.)

(M:M + 0x0001)



(H:X)

–

DIR
EXT
SP1

35
96

9EFF

dd
hh ll
ff

4
5
5

STOP

Enable Interrupts:
Stop Processing
Refer to MCU Documen-
tation

I bit



0; Stop Processing

–

– INH

STX

opr8a

STX

opr16a

STX

oprx16

STX

oprx8

STX ,X
STX

oprx16

,SP

STX

oprx8

,SP

Store X (Low 8 Bits of
Index Register)
in Memory



(X)

–

DIR
EXT
IX2
IX1
IX
SP2
SP1

CF
DF

9EDF

9EEF

dd
hh ll
ee ff
ff

ee ff
ff

3
4
4
3
2
5
4

SUB #

opr8i

SUB

opr8a

SUB

opr16a

SUB

oprx16

SUB

oprx8

SUB ,X
SUB

oprx16

,SP

SUB

oprx8

,SP

Subtract A



(A)

–

(M)

–

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A0
B0

C0
D0

9ED0

9EE0

ii
dd
hh ll
ee ff
ff

ee ff
ff

2
3
4
4
3
3
5
4

SWI

Software Interrupt



(PC) + 0x0001

Push (PCL); SP



(SP) – 0x0001

Push (PCH); SP



(SP) – 0x0001

Push (X); SP



(SP) – 0x0001

Push (A); SP



(SP) – 0x0001

Push (CCR); SP



(SP) – 0x0001



PCH



Interrupt Vector High Byte

PCL



Interrupt Vector Low Byte

–

– INH

TAP

Transfer Accumulator to
CCR

CCR



(A)

INH

TAX

Transfer Accumulator to
X (Index Register Low)



(A)

–

– INH

TPA

Transfer CCR to Accu-
mulator



(CCR)

–

– INH

TST

opr8a

TSTA
TSTX
TST

oprx8

TST ,X
TST

oprx8

,SP

Test for Negative or Zero

(M) – 0x00

(A) – 0x00
(X) – 0x00

(M) – 0x00
(M) – 0x00
(M) – 0x00

–

DIR
INH
INH
IX1
IX
SP1

3D
4D
5D
6D
7D

9E6D

4
1
1
4
3
5

TSX

Transfer SP to Index
Reg.

H:X



(SP) + 0x0001

–

– INH

TXA

Transfer X (Index Reg.
Low) to Accumulator



(X)

–

– INH

TXS

Transfer Index Reg. to
SP



(H:X) – 0x0001

–

– INH

Table 44. HCS08 Instruction Set Summary (Sheet 7 of 8)

Source

Form

Operation

Description

Effect

on CCR

Mode

cod

erand

Bus Cycles

)

V H

N Z C

Summary of Contents for FXTH870 D Series

Page 1: ...34 MHz RF transmitter External crystal oscillator PLL based output with fractional n divider OOK and FSK modulation capability Programmable data rate generator Manchester Bi Phase or NRZ data encoding...

Page 2: ...870502DT1 Z 2264 7 x 7 1 hole lid 100 450 kPa 08 FXTH870511DT1 XZ 2264 7 x 7 1 hole lid 100 450 kPa 0C FXTH870902DT1 Z 2264 7 x 7 1 hole lid 100 900 kPa 18 FXTH870911DT1 XZ 2264 7 x 7 1 hole lid 100 9...

Page 3: ...5 2 MCU Reset 31 5 3 Computer Operating Properly COP Watchdog 31 5 4 SIM Test Register SIMTST 32 5 5 Interrupts 33 5 6 Low Voltage Detect LVD System 36 5 7 System Clock Control 36 5 8 Keyboard Interru...

Page 4: ...12 7 Auto Zero Sequence 95 12 8 Data Recovery 95 12 9 Data Clock Recovery and Synchronization 95 12 10 Manchester Decode 95 12 11 Duty Cycle For Data Mode 96 12 12 Input Signal Envelope 97 12 13 Teleg...

Page 5: ...148 17 3 Electrical Characteristics 149 17 4 Power Consumption MCU 150 17 5 Control Timing 151 17 6 Voltage Measurement Characteristics 152 17 7 Temperature Measurement Characteristics 153 17 8 Press...

Page 6: ...process technology for each Microcontroller with accelerometer and pressure sensor interfaces and RF transmitter MCU Optional ranges on pressure transducers Optional XZ or Z axis acceleration transduc...

Page 7: ...64 Byte PARAMETER REGISTER DATA ENCODE BIT RATE 256 BIT DATA BUFFER RF AMP VCO PLL FRACTL DIVIDER XTAL OSC XI XO RF MCU TRANSDUCERS VOLT REG RESTART OSC GEN PWU TIMER MFO 8 Sec RESET LF RECVR DX VSEN...

Page 8: ...4 fOSC fBUS CPU BDC TPM1 RAM FLASH LFR ADC10 MFO OSC 8 Sec PWU CLSA CLKSB fLFO 1 kHz XTL OSC 26 MHz XI XO PLL VCO BIT RATE DATA BUFFER PRESSURE SENSOR TRANSDUCERS MCU RTICLKS PAR REG fMFO fXCO GEN DX...

Page 9: ...e monitors using the internal PLL based RF output stage is shown in Figure 5 Any of the PTA 3 0 pins can also be used as general purpose I O pins Any of the PTA 3 0 pins that are not used in the appli...

Page 10: ...ositive supply and AVSS is the ground The conductors to the power supply should be connected to the AVDD and AVSS pins and locally decoupled as shown in Figure 6 FXTH870xxx 0 1 F VDD VSS 3 0 V BATTERY...

Page 11: ...FB pins Signaling into the LFR pins can place the FXTH870xD into various diagnostic or operational modes The LFR is comprised of the detector and the decoder Each LF A B pin will always have an impeda...

Page 12: ...istor 10 k which can be over driven by an external signal This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event 2 3 11 RESET Pin The...

Page 13: ...d is received through the BKGD PTA4 pin When a BGND instruction is executed by the CPU When encountering a BDC breakpoint Once in ACTIVE BACKGROUND mode the CPU is held in a suspended state waiting fo...

Page 14: ...pon wakeup from STOP1 mode the MCU will start up as from a power on reset POR by taking the reset vector NOTE If there are any pending interrupts that have yet to be serviced then the device will not...

Page 15: ...e kept alive to the BACKGROUND debug logic clocks to the peripheral systems are halted to reduce power consumption I O Pins If the MCU is configured to go into STOP1 mode the I O pins are forced to th...

Page 16: ...MCU enters any of the STOP modes except STOP4 LVDSE 1 or ENBDM 1 Temperature Sensor The temperature sensor is powered up on command from the MCU Temperature Restart When the MCU enters a STOP mode the...

Page 17: ...ors to the user area from DFC0 through DFFF Any calls to the firmware subroutines are accessed through a jump table starting at location E000 see Section 14 4 2 Reset and Interrupt Vectors Table 2 sho...

Page 18: ...ect addressing mode instructions which requires only the lower byte of the address Bit manipulation instructions can be used to access any bit in any direct page register Table 3 is a summary of all u...

Page 19: ...ADACT ADTRG ACFE ADCFGT 0 0 0 0 002A ADRH 0 0 0 0 ADR 11 8 002B ADRL ADR 7 0 002C ADCVH 0 0 0 0 ADCV 11 8 002D ADCVL ADCV 7 0 002E ADCFG ADLPC ADIV 1 0 ADLSMP MODE 1 0 ADICLK 1 0 002F ADPCTL1 ADPC 7 0...

Page 20: ...7 0 0031 RFCR1 FRM 7 0 0032 RFCR2 SEND RPAGE EOM PWR 4 0 0033 RFCR3 DATA IFPD ISPC IFID FNUM 3 0 0034 RFCR4 RFBT 7 0 0035 RFCR5 BOOST LFSR 6 0 0036 RFCR6 VCO_GAIN 1 0 RFFT 5 0 0037 RFCR7 RFIF RFEF RF...

Page 21: ...EPR VCD3 PLL_LPF_ 2 0 VCD 2 0 PA_SLOPE VCD_EN 0039 Reserved 003A Reserved 003B Reserved 003C RFD0 RFD 135 128 003D RFD1 RFD 143 136 003E RFD2 RFD 151 144 003F RFD3 RFD 159 152 0040 RFD4 RFD 167 160 0...

Page 22: ...any reset provided that the supply voltage does not drop below the minimum value for RAM retention VRAM When security is enabled the RAM is considered a secure memory resource and is not accessible t...

Page 23: ...e writing to the FCDIV register One period of the resulting clock 1 fFCLK is used by the command processor to time program and erase pulses An integer number of these timing pulses are used by the com...

Page 24: ...sing the standard program command This is possible because the high voltage to the FLASH array does not need to be disabled between program operations Ordinarily when a program or erase command is iss...

Page 25: ...software being used Consult tool vendor for programming times START WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD NO YES FPVIOL OR WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF...

Page 26: ...and Writing a second time to FCMD before launching the previous command There is only one write to FCMD for every command Writing to any FLASH control register other than FCMD after writing to a FLASH...

Page 27: ...NVPROT must be programmed to logic 0 to enable block protection Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF Figure 11 Block Protection Mechanism...

Page 28: ...ep in a FLASH program or erase command 2 Writing the user entered key values to the NVBACKKEY through NVBACKKEY 7 locations These writes must be done in order starting with the value for NVBACKKEY and...

Page 29: ...since reset Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written 0 FCDIV has not been written since reset erase and program operation...

Page 30: ...rmware BDM commands cannot be used to write key comparison values that would unlock the backdoor key For more detailed information about the backdoor key mechanism refer to Section 4 8 0 No backdoor k...

Page 31: ...4 FPS3 FPS2 FPS1 FPDIS W 1 1 Background commands can be used to change the contents of these bits in FPROT 1 1 1 1 1 1 1 Reset This register is loaded from nonvolatile location NVPROT during reset Tab...

Page 32: ...uence is not obeyed exactly the erroneous command is ignored if a program or erase operation is attempted before the FCDIV register has been initialized or if the MCU enters STOP while a command was i...

Page 33: ...FXTH870xD has seven sources for reset Power on reset POR Low voltage detect LVD Computer operating properly COP timer Periodic hardware reset PRST Illegal opcode detect Illegal address detect BACKGROU...

Page 34: ...Clock 214 32 768 16 384 8 192 4 096 1 0 1 0 Bus Clock 215 65 536 32 768 16 384 8 192 1 0 1 1 Bus Clock 216 131 072 65 536 32 768 16 384 1 1 0 0 Bus Clock 217 262 144 131 072 65 536 32 768 1 1 0 1 Bus...

Page 35: ...ring the status flag that generated the interrupt so that other interrupts can be serviced without waiting for the first service routine to finish This practice is not recommended for anyone other tha...

Page 36: ...ervice routine is located at the higher address When an interrupt condition occurs an associated flag bit becomes set If the associated local interrupt enable is set an interrupt request is sent to th...

Page 37: ...detected 8 DFEE DFEF Reserved 7 DFF0 DFF1 Vtpm1ovf TPM1 TOF TOIE Interrupt from the TPM1 when the timer overflows 6 DFF2 DFF3 Vtpm1ch1 TPM1 CH1F CH1IE Interrupt from the TPM1 when the selected event...

Page 38: ...for falling and rising differ by a small amount of hysteresis The LVD bit in the SRS register is set following either an LVD reset or POR 5 6 3 LVD Interrupt Operation When a low voltage condition is...

Page 39: ...iting a zero to this bit has no effect Reset clears this bit 0 Wakeup interrupt not generated or was previously acknowledged 1 Wakeup interrupt generated 6 RTIACK Acknowledge RTIF Interrupt Flag The R...

Page 40: ...CU from a very low or a very high temperature is determined by the TRH bit in the SIMOPT1 register 5 11 Reset Interrupt and System Control Registers And Bits One 8 bit register in the direct page regi...

Page 41: ...d or illegal opcode The STOP instruction is considered illegal if STOP is disabled by STOPE 0 in the SOPT register The BGND instruction is considered illegal if ACTIVE BACKGROUND mode is disabled by E...

Page 42: ...er the temperature restart circuit will interrupt the MCU after being shutdown on returning from either a very high or very low temperature This bit is cleared by an MCU reset 0 Temperature restart in...

Page 43: ...LVDF Reads always return logic 0 5 LVDIE Low Voltage Detect Interrupt Enable This read write bit enables hardware interrupt requests for LVDF 0 Hardware interrupt disabled use polling 1 Request a har...

Page 44: ...0 MCU has not recovered from STOP1 mode 1 MCU recovered from STOP1 mode 3 Reserved Reserved Bit This bit is reserved should not be altered by the user Any read returns a logical zero 2 PPDACK Partial...

Page 45: ...erved Bits These bits are reserved for Freescale firmware control Application software shall assure these two bits are never overwritten 5 KBF Keyboard Flag This bit indicates that any keyboard pin ca...

Page 46: ...ated with the shared pins are disabled After reset the shared peripheral functions are disabled so that the pins are controlled by the general purpose I O All of the general purpose I O are configured...

Page 47: ...shared with both an alternate digital function and an analog function the analog function has priority such that if both the digital and analog functions are enabled the analog function controls the p...

Page 48: ...n cases where GPIOs are directly connected to AVDD VDD AVSS VSS or RVSS user application should configure the GPIO as an input with the internal pull up disabled in order to prevent software code faul...

Page 49: ...Table 34 Port A Register Pullup Enable Field Descriptions Field Description 3 0 PTAPE 3 0 Internal Pullup Enable for Port A Bit n Each of these control bits determines if the internal pullup device is...

Page 50: ...figures all port pins as high impedance inputs with pullups disabled 0005 Bit 7 6 5 4 3 2 1 Bit 0 R PTBPE 1 0 W Reset 0 0 0 0 0 0 0 0 Reserved Figure 34 Internal Pullup Enable for Port B Register PTBP...

Page 51: ...de the KBI is disabled In some systems the pins associated with the KBI may be sources of wakeup from STOP1 see the STOP modes section in the Section 3 Upon wakeup from STOP1 mode the KBI module will...

Page 52: ...ted Writes have no effect on KBF 0 No keyboard interrupt detected 1 Keyboard interrupt detected 2 KBACK Keyboard Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism KBACK always re...

Page 53: ...set an interrupt request will be presented to the CPU Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC 7 6 2 Edge and Level Sensitivity A valid edge or level on an enabled KBI pin wil...

Page 54: ...address space 16 bit stack pointer any size stack anywhere in 64 Kbyte address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instructions treat X as...

Page 55: ...tructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed For compatibility with the earlier M68HC05 Family H is forced to 0x00 du...

Page 56: ...ing an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C condi...

Page 57: ...omplete the instruction is included in the object code immediately following the instruction opcode in memory In the case of a 16 bit immediate operand the high order byte is located in the next memor...

Page 58: ...r a more detailed discussion about how the MCU recognizes resets and determines the source refer to the Section 5 The reset event is considered concluded when the sequence to determine whether the res...

Page 59: ...ost debug system is connected to the BACKGROUND DEBUG pin BKGD and the ENBDM control bit has been set by a serial command through the BACKGROUND interface or because the MCU was reset into ACTIVE BACK...

Page 60: ...nded address ll Low order byte of 16 bit extended address rr Relative offset Source form Everything in the source forms columns except expressions in italic characters is literal information that must...

Page 61: ...with Carry A A M C IMM DIR EXT IX2 IX1 IX SP2 SP1 A9 B9 C9 D9 E9 F9 9ED9 9EE9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ADD opr8i ADD opr8a ADD opr16a ADD oprx16 X ADD oprx8 X ADD X ADD oprx16 SP...

Page 62: ...BHCS rel Branch if Half Carry Bit Set Branch if H 1 REL 29 rr 3 BHI rel Branch if Higher Branch if C Z 0 REL 22 rr 3 BHS rel Branch if Higher or Same Same as BCC Branch if C 0 REL 24 rr 3 BIH rel Bran...

Page 63: ...T n opr8a Set Bit n in Memory Mn 1 DIR b0 DIR b1 DIR b2 DIR b3 DIR b4 DIR b5 DIR b6 DIR b7 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 BSR rel Branch to Subroutine PC PC 0x0002 pus...

Page 64: ...h ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 DAA Decimal Adjust Accumulator After ADD or ADC of BCD Values A 10 U INH 72 1 DBNZ opr8a rel DBNZA rel DBNZX rel DBNZ oprx8 X rel DBNZ X rel DBNZ oprx8 SP rel De...

Page 65: ...DX X LDX oprx16 SP LDX oprx8 SP Load X Index Register Low from Memory X M 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 AE BE CE DE EE FE 9EDE 9EEE ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 LSL opr8a LSLA LSLX...

Page 66: ...prx8 SP Rotate Left through Carry DIR INH INH IX1 IX SP1 39 49 59 69 79 9E69 dd ff ff 5 1 1 5 4 6 ROR opr8a RORA RORX ROR oprx8 X ROR X ROR oprx8 SP Rotate Right through Carry DIR INH INH IX1 IX SP1 3...

Page 67: ...ract A A M IMM DIR EXT IX2 IX1 IX SP2 SP1 A0 B0 C0 D0 E0 F0 9ED0 9EE0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 SWI Software Interrupt PC PC 0x0001 Push PCL SP SP 0x0001 Push PCH SP SP 0x0001 Push...

Page 68: ...CC 2 REL 38 5 LSL 2 DIR 48 1 LSLA 1 INH 58 1 LSLX 1 INH 68 5 LSL 2 IX1 78 4 LSL 1 IX 88 3 PULX 1 INH 98 1 CLC 1 INH A8 2 EOR 2 IMM B8 3 EOR 2 DIR C8 4 EOR 3 EXT D8 4 EOR 3 IX2 E8 3 EOR 2 IX1 F8 3 EOR...

Page 69: ...SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 LDX 4 SP2 9EEE 4 LDX 3 SP1 9EFE 5...

Page 70: ...configured for buffered center aligned pulse width modulation CPWM on all channels Clock sources independently selectable Selectable clock sources device dependent bus clock fixed system clock Clock...

Page 71: ...ernal Signal Description When any pin associated with the timer is configured as a timer input a passive pullup can be enabled After reset the TPM1 modules are disabled and all pins default to general...

Page 72: ...after the clear sequence was completed for the earlier TOF Reset clears TOF Writing a 1 to TOF has no effect 0 TPM1 counter has not reached modulo value or overflow 1 TPM1 counter has overflowed 6 TO...

Page 73: ...1MODH TPM1MODL The read write TPM1 modulo registers contain the modulo value for the TPM1 counter After the TPM1 counter reaches the modulo value the TPM1 counter resumes counting from 0x0000 at the n...

Page 74: ...0 to CH0F If another interrupt request occurs before the clearing sequence is complete the sequence is reset so CH0F would remain set after the clear sequence was completed for the earlier CH0F This i...

Page 75: ...er When both bytes have been written they are transferred as a coherent 16 bit value into the timer channel value registers This latching mechanism may be manually reset by writing to the TPM1C0SC reg...

Page 76: ...pt Enable This read write bit enables interrupts from channel 1 Reset clears CH1IE 0 Channel 1 interrupt requests disabled use software polling 1 Channel 1 interrupt requests enabled 5 MS1B Mode Selec...

Page 77: ...lso is associated with the main 16 bit counter in the TPM1 Each TPM1 channel is optionally associated with an MCU pin and a maskable interrupt function The TPM1 has center aligned PWM capabilities con...

Page 78: ...od The 0x0000 count value corresponds to the center of a period Because the HCS08 MCU is an 8 bit architecture a coherency mechanism is built into the timer counter for read operations Whenever either...

Page 79: ...ake effect until the next full period 9 5 3 Center Aligned PWM Mode This type of PWM output uses the up down counting mode of the timer counter CPWMS 1 The output compare value in TPM1CnVH TPM1CnVL de...

Page 80: ...errupt flag is set each time the main timer counter matches the value in the 16 bit channel value register See Section 5 for absolute interrupt vector addresses priority and local interrupt mask contr...

Page 81: ...set each time the main timer counter matches the 16 bit value in the channel value register The flag is cleared by the two step sequence described in Section 9 6 1 9 6 4 PWM End of Duty Cycle Events...

Page 82: ...started and ended synchronously with the sampling of the voltages The accuracy power consumption and timing specifications given in the electrical specifications in Section 17 are based on using the...

Page 83: ...nditions The X axis acceleration is scaled for 20g range within each of the 16 offset steps 10g per step The Z axis acceleration is scaled for 80g range within each of the 16 offset steps 80g or 60g T...

Page 84: ...e determined with the external load resistor connected to VSS VDD1 is the voltage determined with the external load resistor connected to VDD RLOAD is the resistance of the external load resistance in...

Page 85: ...has the option to decide how often each measurement and its component terms are made The resulting power consumption is then the sum of using these components are defined in the electrical specificat...

Page 86: ...FXTH870xD Sensors 84 Freescale Semiconductor Inc Figure 57 Data Flow For Measurements...

Page 87: ...n off all operating functions and enter the STOP1 mode 10 7 3 Temperature Shutdown Recovery The MCU can be restarted by the Temperature Restart TR module when the temperature returns within the normal...

Page 88: ...FXTH870xD Sensors 86 Freescale Semiconductor Inc This sequence is further explained by the user software flowchart in Figure 59 Figure 59 Flowchart for Using TR Module...

Page 89: ...FM crystal oscillator and feeds a 500 kHz clock to the TPM1 for one cycle of the LFO The measured time is used to calculate the correct value for the WDIV 5 0 bits for a WCLK period of 1 second The TP...

Page 90: ...akeup clock WCLK The user can use this prescaler to fine tune the wakeup time based on the variation in the LFO frequency The conversion from the decimal value of the WDIV bits to the nominal WCLK per...

Page 91: ...1 1 1 Reserved Figure 63 PWU Control Status Register 1 PWUCS1 Table 57 PWUSC1 Register Field Descriptions Field Description 7 PRF Periodic Reset Flag The PRF bit indicates when a periodic reset has b...

Page 92: ...dule will cause the MCU to exit the power saving mode as a POR MCU will have the wakeup interrupt pending and once CLI opcode is executed PC will be redirected to wakeup interrupt vector address The W...

Page 93: ...er coded bits at the nominal 3 906 kbps data rate A synchronization pattern is used to mark the boundary between the preamble and the beginning of Manchester encoded information in the message body Th...

Page 94: ...t for the appropriate signal level frequency and duration TPMS protocol verification Data reception 12 3 Power Management In addition to using low power circuit design techniques the LFR module provid...

Page 95: ...ate a carrier is programmed by the LFCDTM register The carrier frequency should be 125 kHz If the signal above the threshold is not within the frequency range or not present during enough time then th...

Page 96: ...WHFW IODJ 6WDUW DQDORJ GHPRGH FKDLQ 502 QFUHPHQW DUULHU RXQWHU DUULHU FRXQWHU DUULHU FRXQWHU 6 RQWLQXRXVO 21 5LVH FDUULHU GHWHFW IODJ 12 6 12 6 QYHUW 502 DWD 5HDG IODJ 7LPHRXW 6 1 HWHFWHG HFRGH URQJ R...

Page 97: ...ty bit in the LFCTRLA register selects the expected encoding of the Manchester data bit If a strong signal above roughly 100 mV p p differential is entered into the LFR the input impedance will switch...

Page 98: ...the relative rise and fall times of the incoming LF carrier as shown in Figure 69 Figure 69 Definition of Duty Cycle of 40 Regarding the SYNC pattern which is non Manchester coded the duty cycle is a...

Page 99: ...ot significantly filter the envelope of the LF carrier as shown in Figure 72 Excessive filtering will cause the received message error rate MER to increase Figure 71 Antenna Q factor Equivalent Model...

Page 100: ...he programmed value selected by the TIMOUT 1 0 bits in the LFCTL4 register This timeout counter is clocked by the internal LFRO clock The LFR can be configured to have an optional 0 8 bit or 16 bit ID...

Page 101: ...of the telegram and turn off the LFR LFEN 0 during two LFO cycles before any other operations 12 15 Continuous ON Mode In the Continuously ON mode the LFR module will remain on continuously while the...

Page 102: ...Enabling the LF receiver function disables the GPIO Port B functions see Section 6 5 6 SRES Soft Reset This read write bit controls the soft reset of the LFR The bit is self reset and always reads as...

Page 103: ...ode every 4096 LFO clock periods 4096 milliseconds nominal 1010 1xxxContinuous ON mode see Section 12 15 3 0 LFONTM 3 0 LF Sampling ON Time Select These read write control bits select the length of ti...

Page 104: ...ut high received signal above threshold 6 TOGMOD LFR Mode Toggle This read write bit enables the toggling of the CARMOD bit at each new LFON sequence Reset clears this bit 0 CARMOD bit does not change...

Page 105: ...he rest of the data Reset of the LFR results in LFCDTM 3 0 being reset to 0 0 0 0 The resulting carrier detect times are defined by the following number of carrier periods needed to validate the carri...

Page 106: ...he LFR detects the number of samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register The LFCDIE is ignored when the LFR is operating in the data mode CARMOD 0 except when DECEN is...

Page 107: ...he MCU if the LFIDIE bit is set Clear LFIDF by writing a one to the LFIAK bit LFIDF is also cleared by reset 0 Normal operation 1 wakeup ID has been detected 3 LFOVF LF Receive Data Overflow Flag In d...

Page 108: ...ecking can be selected or disabled by using the IDSEL 1 0 bits in the LFCTL1 register When ID checking is enabled the ID value received through the LFR must match the contents of the LFIDH and or LFID...

Page 109: ...1 0 SUM AZ release delay Control the delay between falling edge of SUM d_az_en input and falling edge of internal AZ control line 00 No delay 01 No delay 10 One half of 125 kHz clock period delay rec...

Page 110: ...ame as 00 0023 Bit 7 6 5 4 3 2 1 Bit 0 R AMPGAIN 1 0 FINSEL 1 0 AZEN LOWQ 1 0 DEQEN W Reset 1 1 0 0 1 0 0 1 Figure 86 LFR Control Register C LFCTRLC LPAGE 1 Table 68 LFCTRLC Register Field Description...

Page 111: ...ng and control offset value 00 Standard low pass filtering activated recommended setting 01 Standard low pass filtering activated 10 Bi phase filtering activated Low offset from input signal low level...

Page 112: ...he carrier detect sample ON time detected an LF carrier signal before the LFCDF flag bit set The flag will be risen when the number of ON samples with a detected carrier greater than the LFCDTM 3 0 re...

Page 113: ...ware while the MCU can be put into a low power mode until the transmission is completed This RF state machine is clocked by the MFO which is enabled when the SEND bit is set and when any of the LFR SM...

Page 114: ...is controlled directly by the MCU where the data to the RF output depends on the state of the DATA bit and the selected modulation scheme In this mode the user software must control the RF output sta...

Page 115: ...bit is set 13 2 2 End of Message EOM If the EOM control bit is set then at the end of the data frame there will be carrier for a period of two bit times at level high for the OOK modulation modes or...

Page 116: ...MCU or using this interval timing generator Figure 92 Initial and Interframe Timing SPACE SPACE t0 Time Not To Scale SPACE Interframe Intervals 1 to 16 Data Frames With Identical Data Start of Time In...

Page 117: ...rames The programmable frame space interval is based on a simple 8 bit count down timer as described by the RFBT 7 0 control bits in the RFCR4 register This time interval is forced to zero when the RF...

Page 118: ...es is defined by the FNUM 3 0 control bits The range of the frame number time is a multiple of 0 to 63 ms using a clock generated from the MFO divided by 125 The value of this time multiple can be cha...

Page 119: ...ng When the CODE 1 0 bits are 0 1 then the data is Bi Phase encoded format with data transmitted as the presence or absence of a transition in signal in the middle of the bit time The polarity of this...

Page 120: ...anchester Data Bit Encoding POL 1 LOW BIT HIGH BIT FSK fRF f FSK fRF f Bit Time Consecutive 0 Data Bits Consecutive 1 Data Bits 001101 Data Bits OOK fRF OOK OFF Bit Time LOW BIT HIGH BIT FSK fRF f FSK...

Page 121: ...The modulation control bit MOD described in Section 13 18 sets the modulation of the RF signal will be either amplitude shift keying OOK or frequency shift keying FSK with several options for the freq...

Page 122: ...bit The RFVF bit can be cleared by writing a logical one to the RFIAK bit if the supply voltage has risen above the detect threshold Further if the voltage falls far enough for the VCO and PLL to fal...

Page 123: ...ns Field Description 7 0 BPS 7 0 Data Rate The BPS 7 0 control bits select the data rate for the transmitted datagrams as described by the following equation where fDATA Data rate in bits second fXTAL...

Page 124: ...a held in the RFM data buffer according to the bit length specified by the FRM 7 0 bits The SEND control bit is automatically cleared when the data buffer transmission has ended or by the RFMRST signa...

Page 125: ...power level to 1 0 dBm 00011 set output power level to 0 5 dBm 00100 set output power level to 0 0 dBm 00101 set output power level to 0 5 dBm 00110 set output power level to 1 0 dBm 00111 set output...

Page 126: ...where the power step is adjusted to guarantee a minimum of 3 dBm as shown in Figure 101 The power consumption in this domain is given as the maximum consumption at whatever temperature of supply volta...

Page 127: ...ming events The restart of these functions will start 1 ms before the end of the timing interval if another frame is to be transmitted 5 ISPC Initial Random Space When the ISPC bit is set the initial...

Page 128: ...5 Register Pseudo Random Time Variable Table 79 RFCR5 Field Descriptions Field Description 7 BOOST BOOST This bit controls the VCO power consumption in order to decrease the phase noise required by th...

Page 129: ...only RFIF status bit indicates if the RF transmission has ended properly when using the data buffer mode and the SEND bit has been cleared Writes to this bit will be ignored The RFIF status bit is cl...

Page 130: ...ffect 1 Reset RFM 0038 Bit 7 6 5 4 3 2 1 Bit 0 R AFREQ 12 5 W RFMRST 0 0 0 0 0 0 0 0 0039 R AFREQ 4 0 POL CODE W RFMRST 0 0 0 0 0 0 0 0 Figure 107 PLL Control Registers A PLLCR 1 0 RPAGE 0 Table 82 PL...

Page 131: ...ta one in either the OOK or FSK modes of modulation as described by the following equation where fCARRIER RF Carrier frequency in MHz fXTAL External crystal frequency in MHz CF State of the CF carrier...

Page 132: ...LPF_ 2 0 Low Pass Filter Selection These read write bits select the PLL low pass filter A reset sets these bits to 03 These bits are only accessible if the VCD_EN bit is clear 7 4 VCD 3 0 VCO Calibrat...

Page 133: ...7 160 for RPAGE 1 0041 RFD 47 40 for RPAGE 0 RFD 175 168 for RPAGE 1 0042 RFD 55 48 for RPAGE 0 RFD 183 176 for RPAGE 1 0043 RFD 63 56 for RPAGE 0 RFD 191 184 for RPAGE 1 0044 RFD 71 64 for RPAGE 0 RF...

Page 134: ...is used as the reference frequency for the VCO calibration in OOK mode MOD 0 Calibration occurs every time the VCO is enabled The calibration takes approximately 5 s The state machine of the calibrat...

Page 135: ...eWarrior project file that is supplied by Freescale Any future updates to these firmware routines will be contained in that file A summary of the firmware routines available is given in Table 86 The f...

Page 136: ...nd wires E066 TPMS_FLASH_WRITE Write to FLASH E069 TPMS_FLASH_CHECK Performs checksum on Freescale firmware FLASH E06C TPMS_FLASH_ERASE Erases one page 512 bytes of FLASH at a time E06F TPMS_READ_DYNA...

Page 137: ...der E048 TPMS_RF_WRITE_DATA Write RFM data buffer E04B TPMS_RF_WRITE_DATA_REVERSE Write RFM data buffer in reverse bit order E04E TPMS_RF_CONFIG_DATA Configure RFM E051 Reserved Reserved E054 TPMS_RF_...

Page 138: ...description CODE1 7 5 ES Revision number for the multiple chip module silicon 000 MCU version 0 111 MCU version 7 CODE1 4 PRESS H Calibrated range for pressure The range is a combination of this bit a...

Page 139: ...numbers between 0 and 1023 These digital numbers will have corresponding DINMIN DINLO DINHI DINMAX values The ADC10 digital value is taken by the firmware and compensated and scaled to give the requir...

Page 140: ...overflow rule mentioned above is used 14 3 Memory Resource Usage The firmware uses the top 8192 bytes of the FLASH memory map The firmware uses no specific bytes of the RAM but will cause additional...

Page 141: ...OUND mode commands allow the CPU registers to be read or written and allow the user to trace one user instruction at a time or GO to the user program from ACTIVE BACKGROUND mode Non intrusive commands...

Page 142: ...r reset The specific conditions for forcing ACTIVE BACKGROUND depend upon the HCS08 derivative refer to the introduction to this Development Support section It is not necessary to reset the target MCU...

Page 143: ...shows the host receiving a logic 0 from the target HCS08 MCU Because the host is asynchronous to the target MCU there is a 0 to 1 cycle delay from the host generated falling edge on BKGD PTA4 to the s...

Page 144: ...begin with an 8 bit hexadecimal command code in the host to target direction most significant bit first separates parts of the command d delay 16 target BDC clock cycles AAAA a 16 bit address in the...

Page 145: ...s just read and report status WRITE_BYTE Non intrusive C0 AAAA WD d Write a byte to target memory WRITE_BYTE_WS Non intrusive C1 AAAA WD d SS Write a byte and report status READ_BKPT Non intrusive E2...

Page 146: ...truction queue This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address The breakpoint enable BKPTEN control b...

Page 147: ...d enter ACTIVE BACKGROUND mode if CPU attempts to execute that instruction 1 Breakpoint match forces ACTIVE BACKGROUND mode at next instruction boundary address need not be an opcode 3 CLKSW Select So...

Page 148: ...oint logic in the BDC refer to Section 15 2 4 15 3 4 System Background Debug Force Reset Register SBDFR This register contains a single write only control bit A serial BACKGROUND mode command such as...

Page 149: ...pressure measurements over lifetime nTEMP Total number of temperature measurements over lifetime nVOLT Total number of voltage measurements over lifetime 16 3 Transmission Events The overall charge co...

Page 150: ...D PTA4 RESET LFA LFB IIN IIN IIN IIN 10 10 10 10 mA mA mA mA 3 3 3 3 109 110 Substrate Current Injection Current from any pin to VSS 0 3 VDC XI PTA0 PTA1 PTA2 PTA3 PTB0 PTB1 BKGD PTA4 RESET LFA LFB IS...

Page 151: ...VDD 2 3 PTA0 PTA1 PTA2 PTA3 PTB0 PTB1 BKGD PTA4 VIH VIH 0 7 x VDD 0 85 x VDD V V 2 3 304 305 Input Low Voltage 2 3 VDD VH PTA0 PTA1 PTA2 PTA3 PTB0 PTB1 BKGD PTA4 Input Low Voltage VL VDD 2 3 PTA0 PTA1...

Page 152: ...on TA 40 C VDD 3 0 V TA 0 C VDD 3 0 V TA 25 C VDD 1 8 V TA 25 C VDD 3 0 V TA 70 C VDD 3 0 V TA 125 C 3 0 V VDD 3 6 V ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 73 100 100 95 95 100 140 A A A A A...

Page 153: ...4 MCU Bus Frequency fBUS 0 5 fOSC MHz 2 505 Medium frequency clock MFO Full temperature range 40 C to 125 C fMFO 106 128 kHz 3 506 Low frequency clock LFO Full temperature range 40 C to 125 C fLFO 770...

Page 154: ...60 1 79 1 95 V 2 613 Voltage drop detection time note 16 tLVDRF 10 sec 3 614 615 Power On Reset Voltage note 15 Rising Voltage to Recover Falling Voltage to Reset VPORR VPORF 0 8 2 1 V V 3 3 616 617 6...

Page 155: ...C C C C count 3 3 1 3 3 3 1 3 3 3 710 Temperature measurement stability range note 10 TSTAB 2 count 3 711 712 713 714 Thermal Shutdown Recovery TRE 1 High Re Arming Temperature TRH 1 note 13 High Rese...

Page 156: ...0 255 499 510 511 20 C TA 0 C 70 C TA 85 C PCODE 0 1 10 255 499 510 511 40 C TA 20 C 85 C TA 125 C PCODE 0 1 10 255 499 510 511 P P P P P P P P P P P P P P P P P P P P P 93 100 268 436 443 89 5 96 5 2...

Page 157: ...6 869 885 76 92 477 860 876 FAULT 100 116 501 884 900 FAULT FAULT 100 116 501 884 900 FAULT FAULT 100 116 501 884 900 FAULT 110 126 511 894 910 115 131 516 899 915 124 140 525 908 924 kPa kPa kPa kPa...

Page 158: ...the following to calculate the sensitivity for offset step 6 Eqn 16 Once the sensitivity AZ 6 has been calculated the acceleration AZ can be calculated with the following transfer function Eqn 17 Ano...

Page 159: ...4 5 4 count 3 1008 1009 1010 1011 Minimum range of acceleration measurement for each offset code Average Offset STEP 0 ACODE 1 256 510 A0 304 215 271 231 191 238 167 210 180 150 80 70 60 g 3 1012 101...

Page 160: ...256 510 A14 240 317 275 319 362 310 408 210 240 270 60 70 80 g 3 1068 1069 1070 1071 Offset STEP 15 ACODE 1 256 510 A15 274 350 315 359 402 356 455 240 270 300 70 80 90 g 3 2 3 VDD 3 6 20 C TA 85 C u...

Page 161: ...0 CHK125 00 Detect level LFA B No detect level LFA B SDET_VL SNODET_VL SDET_L SNODET_L SDET_H SNODET_H SDET_H SNODET_H 24 2 0 5 0 12 0 12 60 14 3 5 mV p p mV p p mV p p mV p p mV p p mV p p mV p p mV...

Page 162: ...ALEN 1 LFCDTM 256 sec Always accepted carrier Always rejected carrier low band limit Always rejected carrier high band limit VALEN 0 LFCDTM 256 ms High Cutoff Freq 5 mV p p input SENS 1 0 00 fLFC fLFC...

Page 163: ...uit VAS LS VLFIN ZS Pad leakage due to input protection SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT RADIN Input SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection RADIN SIMPLIFIED CHANN...

Page 164: ...AFREQ 12 0 and BFREQ 12 0 fSTEP 3 174 kHz 3 1407 External Crystal Frequency note 14 fXTAL 26 000 MHz 3 1408 Fixed portion of RF start process tS RCTS 300 sec 3 1409 Variable portion of RF start proce...

Page 165: ...it sec and for OOK up to 9600 bit sec Analyzed setup RBW VBW up to 10 kHz Span up to 1 25 MHz and MaxHold NPH NPH NPH NPH NPH NPH NSPUR OBWK 86 92 84 84 89 82 45 78 86 82 76 83 80 40 180 dBc Hz dBc Hz...

Page 166: ...acteristic Symbol Min Typ Max Units 1500 1501 1502 1503 1504 1505 1506 1507 1508 RF Supply Transmission Current VDD 3 0 V PWR 4 0 set for nominal 5 dBm 315 MHZ Power delta for BOOST 1 315 MHZ Carrier...

Page 167: ...V 3 6V 3dBm 3dBm 3V 6 3mA 6 5mA 5 5mA 5 7mA 6 7mA 6 8mA 7 8mA 7 1mA 6 4mA 6 8mA 6 6mA 40 C 125 C 25 C 60 C 0 C 3dBm 5dBm 1 8V 2 5V 3 6V 3dBm 3dBm 3V 6 3mA 6 5mA 5 5mA 5 7mA 6 7mA 6 8mA 7 8mA 7 1mA 6 4...

Page 168: ...port pointing inward care must be taken to assure contaminants do not reach inside the pressure port A plugged port will exhibit no change in pressure and can be cross checked in the user s software u...

Page 169: ...voltage change rates less than 20 mV s Hysteresis thresholds may decrease above 85 C 16 Response time to VDD of more than 100 mV below the minimum VDD falling threshold 17 Crystal oscillator margin i...

Page 170: ...FXTH870xD Sensors 168 Freescale Semiconductor Inc 19 Package Outline Figure 127 QFN Case Outline...

Page 171: ...FXTH870xD Sensors Freescale Semiconductor Inc 169 Figure 128 QFN Case Outline...

Page 172: ...FXTH870xD Sensors 170 Freescale Semiconductor Inc Figure 129 QFN Case Outline...

Page 173: ...FXTH870xD Sensors Freescale Semiconductor Inc 171...

Page 174: ...e GPIO pins to Seven multipurpose GPIO pins and sub bullets Section 2 3 8 Updated paragraph with additional content Section 2 3 9 Updated title and paragraphs with corrected pin numbers and added text...

Page 175: ...or line 1802 Notes page Updated Notes 2 18 19 20 and added note 25 Rev 1 3 01 2015 Section 17 3 Updated Characteristic column for lines 303 305 307 308 310 and 311 Changed note reference for lines 306...

Page 176: ...ng without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual pe...

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