2308-900-01 Rev. A / July 2008
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Section Topics
7-3
Model 2308 Portable Device Battery/Charger Simulator User’s Manual
Section 7: Status Structure
Figure 7-1
Status model structure
Clearing registers and queues
When the power supply is turned on, the bits of all registers in the status structure are clear (reset
to 0) and the two queues are empty. Commands to reset the event and event enable registers, and
the error queue are listed in
Table 7-1
. In addition to these commands, any enable register can be
reset by sending the 0 parameter value with the individual command to program the register.
NOTE
*RST
has no effect on status structure registers and queues. See
Queues
for
details on the error queue
.
3
5
6
Cal
9
10
11
12
13
14
15
Condition
Regist
(Always Zero)
3
5
6
9
10
11
12
13
15
Even
Regist
3
5
6
9
10
11
12
13
15
Even
Enabl
Regist
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
O
11
12
13
15
Condition
Regist
Even
Regist
Even
Regist
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
O
EA
QS
MAV
ES
RQS/MS
OS
Statu
Byt
Regist
1
EA
QS
MAV
ES
6
OS
Servic
Reque
Enabl
Regist
&
&
&
&
&
&
&
Logical
O
*STB
*SR
*SR
Master Summary Status
MSB = Measurement Summary Bit
EAV = Error Available
QSB = Questionable Summary Bit
MAV = Message Available
ESB = Event Summary
RQS/MSS = Request for Service/Master Summary
OSB = Operation Summary Bit
Error Queue
Output Queue
Note
: RQS bit is in serial poll byte,
MSS bit is in *STB? response.
1
14
14
OP
QY
DDE
EX
CM
URQ
PON
8
9
11
12
13
15
Regist
8
9
11
12
13
15
Regist
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
O
(Always Zero)
Operation Complete
Query Error
Device Specific Error
Execution Error
Command Error
User
Power On
OP
QY
DDE
EX
CM
URQ
PON
*ES
*ES
MS
MS
12
13
14
15
(Always Zero)
Even
Regist
Even
Enabl
Regist
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Logical
O
Condition
Regist
1
1
Calibration Summary
0
9
11
4
4
4
0
1
2
0
1
2
0
1
2
7
14
:CONDition?
[:EVENt]?
:ENABle <NRf>
:ENABle?
Questionable Event Registers
14
14
10
10
*ESE <NRf>
Event
Event Enable
Standard Event Registers
BF1
Pulse Trigger Timeout Channel 1
PTT1
Reading Overflow Channel 1 ROF1
2
1
0
:CONDition?
[:EVENt]?
:ENABle <NRf>
:ENABle?
CL1
CLT1
PSS
10
Current Limit Tripped 1
Power Supply Shutdown
(Always Zero)
VPT1
Current Limit 1
:CONDition?
[:EVENt]?
:ENABle <NRf>
:ENABle?
Operation Event Registers
Cal
7
Cal
7
Measurement Event Registers
12
13
14
15
11
2
1
0
12
13
14
15
11
2
1
0
14
11
12
13
15
0
9
PSS
10
14
11
12
13
15
0
9
PSS
10
VPT Channel 1
VPT Channel 2 VPT2
Heat Sink Shutdown
Current Limit 2
Reading Available Channel 1
Reading Overflow Channel 2
Reading Available Channel 2
Buffer Full Channel 1
Buffer Full Channel 2
RAV1
BF2
PTT2
ROF2
RAV2
Pulse Trigger Timeout Channel 2
BF1
PTT1
ROF1
RAV1
BF2
PTT2
ROF2
RAV2
BF1
PTT1
ROF1
RAV1
BF2
PTT2
ROF2
RAV2
CL2
VPT1
VPT2
VPT1
VPT2
CL1
CL1
CLT1
CLT1
HSS
HSS
HSS
CL2
CL2
Current Limit Tripped 2 CLT2
CLT2
CLT2
Summary of Contents for 2308
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