Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
94
Order Number: 317805-001US
2.7
ATU Error Conditions
PCI and internal bus error conditions cause ATU state machines to exit normal
operation and return to idle states. In addition, status bits are set to inform error
handling code of exact cause of error condition. Error conditions and status can be
found in the ATUSR. The basic flow for a PCI error is as follows:
• Set the bit in the ATU Status Register which corresponds to the error condition
(master abort, target abort, etc.)
• Set the bit in the ATU Interrupt Status Register which corresponds to the error
condition (master abort, target abort, etc.). This function is maskable for all PCI
error conditions.
• The setting of the bit in the ATU Interrupt Status Register results in an interrupt
being driven to the Intel XScale
®
processor.
Error conditions on one side of the ATU are generally propagated to the other side of
the ATU and have different effects depending on the error. Error conditions and their
effects are described in the following sections.
PCI bus error conditions and the action taken on the bus are defined within the PCI
Local Bus Specification, Revision 2.3, and the PCI-X Protocol Addendum to the PCI
Local Bus Specification, Revision 2.0. The ATU adheres to the error conditions defined
within the PCI specification for both requester and target operation. Error conditions on
the internal bus are caused by an ECC error from the Memory Controller, (see
Section
8.4, “ECC Interrupts/Error Conditions” on page 531
for details on memory controller
error conditions), an Internal Bus Byte Parity Error, or by incorrect addressing resulting
in an internal master abort. All actions on the PCI Bus for error situations are
dependent on the error control bits found in the ATU Command Register (see
Section
2.14.5, “ATU Command Register - ATUCMD” on page 148
) for both Conventional and
PCI-X modes. For PCI-X mode, the error response is also dependent on an error control
bit in the PCI-X Command Register (see
Section 2.14.55, “PCI-X Command Register -
PCIXCMD” on page 191
). In addition, for PCI-X Mode 2 only, the error response also
depends on the ECC Control and Status Register (see
Section 2.14.57, “ECC Control
and Status Register - ECCCSR” on page 195
).
The 4138xx operates in parity mode (when enabled) for conventional PCI (PCI-33,
PCI-66), and PCI-X Mode 1 (PCI-X 66, PCI-X 133). For PCI-X Mode 2, the 4138xx
functions in ECC mode. Parity errors, single-bit ECC errors (when correction is
disabled), and multi-bit ECC errors are uncorrectable errors. In ECC mode, all single-bit
errors are corrected when error correction is enabled and the transaction completes.
The following sections detail all ATU error conditions on the PCI and 4138xx internal
bus, action taken on these conditions, and status and control bits associated with error
handling.
