Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
230
Order Number: 317805-001US
3.0
Address Translation Unit (PCI Express)
This chapter describes the operation modes, setup, and implementation of the module
which interfaces between the PCI Express Link and the Intel
®
413808 and 413812 I/O
Controllers (4138xx) internal bus.
3.1
Overview
As indicated in
Figure 22
, the Address Translation Unit (ATU) — the interface between
the PCI Express Link and the on-chip internal bus — consists of the Address Translation
Unit (ATU) and the Expansion ROM Unit.
The ATU supports both inbound and outbound address translation. The ATU provides
access between the PCI Express Link and the 4138xx internal bus.
Transactions initiated on the PCI Express Link and targeted at the 4138xx internal bus
are referred to as inbound transactions (PCI Express to internal bus). Transactions
initiated on the 4138xx internal bus and targeted at the PCI Express Link are referred
to as outbound transactions (internal bus to PCI Express). The ATU accepts multiple
inbound or outbound transactions and processes them simultaneously.
During inbound transactions, the ATU converts PCI addresses (initiated by a PCI
Express Requester) to internal bus addresses and initiates the data transfer on the
4138xx internal bus. During outbound transactions, the ATU converts internal bus
addresses to PCI addresses and initiates the data transfer on the PCI Express Link.
The Expansion ROM provides the PCI mechanism for downloading device/board driver
code during system boot sequence. It consists of a separate inbound address range
which accesses a Flash EPROM device connected through the 4138xx memory
controller. Refer to the PCI Local Bus Specification, Revision 2.3 for details of Expansion
ROM usage.
The Address Translation Unit and the Expansion ROM Translation Unit represent a single
function of the multi-function 4138xx device.
The ATU supports the following PCI Express Lane widths and frequencies delivering up
to 4096 Mbytes/sec of bandwidth:
— Lane Widths: x8, x4, x2, x1
— Link Frequency: 2.5Gbits/s
All PCI Express transactions are protected by link layer CRC.
On the internal interface, the ATU implements the 4138xx internal bus protocol which
provides for a maximum of 4800 Mbytes/sec of bandwidth.
Address and data are protected by byte-wise parity on the internal bus.
