Intel
®
413808 and 413812—Contents
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
16
Order Number: 317805-001US
10.7.26Interrupt Priority Register 1 — IPR1 ........................................................620
10.7.27Interrupt Priority Register 2 — IPR2 ........................................................621
10.7.28Interrupt Priority Register 3 — IPR3 ........................................................622
10.7.29Interrupt Priority Register 4 — IPR4 ........................................................623
10.7.30Interrupt Priority Register 5 — IPR5 ........................................................624
10.7.31Interrupt Priority Register 6 — IPR6 ........................................................625
10.7.32Interrupt Priority Register 7 — IPR7 ........................................................626
11.0 Timers.....................................................................................................................627
11.1 Timer Operation ..............................................................................................628
11.1.1 Basic Programmable Timer Operation ......................................................628
11.1.2 Watch Dog Timer Operation ...................................................................629
11.1.3 Load/Store Access Latency for Timer Registers .........................................630
11.2 Timer Interrupts..............................................................................................631
11.3 Timer State Diagram........................................................................................632
11.4 Timer Registers ...............................................................................................633
11.4.1 Power Up/Reset Initialization..................................................................633
11.4.2 Timer Mode Registers – TMR0:1 .............................................................634
11.4.2.1 Bit 0 — Terminal Count Status Bit (TMRx.tc)...............................635
11.4.2.2 Bit 1 — Timer Enable (TMRx.enable)..........................................635
11.4.2.3 Bit 2 — Timer Auto Reload Enable (TMRx.reload).........................635
11.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri) ...636
11.4.2.5 Bits 4, 5 — Timer Input Clock Select (TMRx.csel1:0)....................636
11.4.3 Timer Count Register – TCR0:1 ..............................................................637
11.4.4 Timer Reload Register – TRR0:1 .............................................................637
11.4.5 Timer Interrupt Status Register – TISR....................................................638
11.4.6 Watch Dog Timer Control Register – WDTCR ............................................639
11.4.7 Watch Dog Timer Setup Register – WDTSR ..............................................639
11.5 Uncommon TCRX and TRRX Conditions...............................................................640
12.0 SMBus Interface Unit.................................................................................................641
12.1 Overview........................................................................................................641
12.2 SMBus Interface ..............................................................................................641
12.3 System Management Bus Interface ....................................................................642
12.3.1 SMBus Controller..................................................................................643
12.3.1.1 SMBus Commands...................................................................643
12.3.1.2 Initialization Sequence.............................................................644
12.3.2 SMBus Signaling...................................................................................645
12.3.2.1 Overview ...............................................................................645
12.3.2.2 Waveforms.............................................................................645
12.3.2.2.1 Start Phase ....................................................................... 645
12.3.2.2.2 Stop Phase........................................................................ 646
12.3.2.2.3 ACK/NACK........................................................................ 646
12.3.2.2.4 Wait States........................................................................ 646
12.3.3 Architecture.........................................................................................647
12.3.3.1 Data Transfer Examples ...........................................................649
12.3.3.2 Configuration and Memory Reads ..............................................649
12.3.3.3 Configuration and Memory Writes..............................................652
12.3.4 Error Handling......................................................................................654
12.3.5 SMBus Interface Reset ..........................................................................654
12.4 Register Definitions..........................................................................................655
12.4.1 SMBus Controller Command Register — SM_CMD......................................655
12.4.2 SMBus Controller Byte Count Register — SM_BC.......................................656
12.4.3 SMBus Controller ADDR3 Register — SM_ADDR3.......................................656
12.4.4 SMBus Controller ADDR2 Register — SM_ADDR2.......................................656
12.4.5 SMBus Controller ADDR1 Register Number — SM_ADDR1...........................657
