Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
67
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.2
Outbound Transactions- Single Address Cycle (SAC) Internal
Bus Transactions
Outbound transactions initiated by the 4138xx core processor are directed to the PCI
interface through the ATU. The core processor always generates Single Address Cycles
on the internal bus. As a PCI master, the ATU is capable of PCI I/O transactions, PCI
memory reads (in case of conventional PCI), memory read DWORD (in case of PCI-X),
PCI memory writes, configuration reads and writes, and DAC cycles. Outbound memory
transactions are always attempted as 64-bit PCI transactions. Outbound memory write
operations are performed as posted operations and outbound memory read operations
are all performed as split read operations.
Outbound transactions use a separate set of queues from inbound transactions.
Outbound write operations have their address entered into the outbound write address
queue (OWADQ) and their data into the outbound write queue (OWQ). Outbound read
transactions, performed as split transactions, use the Outbound Transaction Queue
(OTQ) to store address, and get data returned into the outbound read queue (ORQ).
Refer to
Section 2.6.2
for details of outbound queue architecture. Outbound
configuration transactions use a special outbound port structure. Refer to
Section 2.2.3
for details.
For outbound write transactions, the ATU is a target on the internal bus and initiator on
the PCI bus. For outbound read transactions, the ATU is a completer on the internal bus
(initially accepts the split read as a target and then provides read data by initiating a
split completion). Internal bus operation is defined in
Chapter 7.0, “System Controller
(SC) and Internal Bus Bridge”
. ATU specific internal bus operation is defined in
Section 2.2.6
.
