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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

261

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.8

ATU Queue Architecture

ATU operation and performance depends on queueing mechanism implemented

between internal bus interface and PCI Express interface.

Figure 23

indicates the ATU

queue architecture consists of separate inbound and outbound queues. The function of

each queue is described in the following sections.

3.8.1

Inbound Queues

The inbound data queues of the ATU support transactions initiated on a PCI Express

Link and targeted at either 4138xx local memory or a 4138xx memory mapped

Table 126

details the name and sizes of the ATU inbound data queues.

3.8.1.1

Inbound Posted Queue Structure

The ATU Inbound Posted Queues consist of the inbound posted data queue (IPDQ) and

the inbound posted header queue (IPHQ). The inbound posted data queue holds the

data for posted (memory/message) transactions moving from a PCI Express Link to the

internal bus and the header queue holds the corresponding address. The inbound

posted data queue has a queue depth of 4 KBytes and moves posted transactions from

the PCI Express Link to the internal bus. The corresponding header queue, IPHQ, is

capable of holding 8 entries.
The following rules apply to the PCI Express Link interface and govern the acceptance

of data into inbound posted queues:

• Posted transactions are drained from the head of the queue when the master

interface has acquired bus ownership and transaction ordering and priority have

been satisfied (see

Section 3.8.3

). A memory write transaction is considered

drained from the queue when the entire amount of data entered on the PCI Express

Link has been accepted by the internal bus target. Error conditions resulting in the

cancellation of a write transaction only flush the transaction at the head of the data

and address queue. All other transactions within the queues are considered still

valid.

Table 126. Inbound Queues

Queue Mnemonic

Queue Name

Queue Size

(Bytes)

IPDQ

Inbound Posted Data Queue

3.75 KBytes (240 credits)

IPHQ

Inbound Posted Header Queue

16 Headers

INPQ

Inbound Non Posted Queue

8 Headers

a. Non Posted request with data (I/O and Configuration Writes) always use the 3DW header. The

associated data is always 1 DW in size and can be stored the 4th DW of the header queue.

ICPLDQ

Inbound Completion Data Queue

4 KBytes (infinite credits)

b. As a PCI Express endpoint the ATU must pre-allocate buffer space before issuing a read request. The

ATU is required to advertise infinite credits.

ICPLHQ

Inbound Completion Header Queue

4 Headers (infinite)

Summary of Contents for 413808 I/O

Page 1: ...Order Number 317805 001US Intel 413808 and 413812 I O Controllers in TPER Mode Developer s Manual October 2007...

Page 2: ...terized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which ha...

Page 3: ...ocessor Communication 47 1 5 15 Inter Processor Messaging Unit 47 1 5 16 Timers 47 1 5 17 GPIO 47 1 5 18 FSENG 47 1 6 Terminology and Conventions 48 1 6 1 Representing Numbers 48 1 6 2 Fields 48 1 6 3...

Page 4: ...terface 97 2 7 3 1 Outbound Read Request Uncorrectable Data Errors 98 2 7 3 1 1 Immediate Data Transfer 98 2 7 3 1 2 Split Response Termination 99 2 7 3 2 Outbound Write Request Uncorrectable Data Err...

Page 5: ...uest 115 2 7 9 1 2 Inbound Read Request 116 2 7 9 2 Target Abort on the Internal Bus 117 2 7 9 2 1 Conventional Mode 117 2 7 9 2 2 PCI X Mode 117 2 7 9 3 Parity Error on the Internal Bus 118 2 7 9 3 1...

Page 6: ...Translate Value Register 1 IATVR1 172 2 14 33Inbound ATU Upper Translate Value Register 1 IAUTVR1 172 2 14 34Inbound ATU Limit Register 2 IALR2 173 2 14 35Inbound ATU Translate Value Register 2 IATVR...

Page 7: ...81Outbound Configuration Cycle Function Number OCCFN 219 2 14 82PCI Interface Error Control and Status Register PIECSR 220 2 14 83PCI Interface Error Address Register PCIEAR 221 2 14 84PCI Interface E...

Page 8: ...268 3 8 4 1 Parity Generation 268 3 8 4 2 Parity Checking 269 3 8 4 3 Parity Disabled 269 3 9 ATU Error Conditions 270 3 9 1 PCI Express Errors 271 3 9 1 1 Role Based Error Reporting 271 3 9 1 2 Malf...

Page 9: ...slate Value Register 0 IAUTVR0 319 3 17 31Inbound ATU Limit Register 1 IALR1 320 3 17 32Inbound ATU Translate Value Register 1 IATVR1 321 3 17 33Inbound ATU Upper Translate Value Register 1 IAUTVR1 32...

Page 10: ...DW Register DSN_LDW 365 3 17 85Device Serial Number Upper DW Register DSN_UDW 365 3 17 86PCI Express Advisory Error Control Register PIE_AEC 366 3 17 87Power Budgeting Enhanced Capability Header PWRB...

Page 11: ...2 MSI X Capability and Table Structures 407 4 6 3 Level Triggered Versus Edge Triggered Interrupts 409 4 7 Register Definitions 410 4 7 1 Inbound Message Register IMRx 412 4 7 2 Outbound Message Regis...

Page 12: ...n Lower Address Register H2L_DLAR 452 5 4 9 HostToLocal Source Upper Address Register H2L_SUAR 453 5 4 10 HostToLocal Source Lower Address Register H2L_SLAR 453 5 4 11 HostToLocal Byte Count Register...

Page 13: ...rnal Bus Data Test Control Register SIBDTCR 502 7 5 4 Peripheral Memory Mapped Register Base Address Register PMMRBAR 503 7 5 5 Determining Block Sizes for Memory Windows 504 7 5 6 Bridge Window Base...

Page 14: ...ter SECAR 540 8 6 7 SRAM ECC Test Register SECTST 541 8 6 8 SRAM Parity Control and Status Register SPARCSR 542 8 6 9 SRAM Parity Address Register SPAR 543 8 6 10 SRAM Parity Upper Address Register SP...

Page 15: ...r Interrupts 579 10 5 7 Intel XScale Processor Interrupts 579 10 5 8 Software Interrupts 579 10 6 Default Status 580 10 7 Interrupt Control Unit Registers 581 10 7 1 Interrupt Base Register INTBASE 58...

Page 16: ...pri 636 11 4 2 5 Bits 4 5 Timer Input Clock Select TMRx csel1 0 636 11 4 3 Timer Count Register TCR0 1 637 11 4 4 Timer Reload Register TRR0 1 637 11 4 5 Timer Interrupt Status Register TISR 638 11 4...

Page 17: ...668 13 4 1 UART x Receive Buffer Register 670 13 4 2 UART x Transmit Holding Register 670 13 4 3 UART x Interrupt Enable Register 671 13 4 4 UART x Interrupt Identification Register 672 13 4 5 UART x...

Page 18: ...Support 723 15 1 1 General Purpose Inputs 723 15 1 2 General Purpose Outputs 723 15 1 3 Reset Initialization of General Purpose I O Function 723 15 2 Register Definitions 724 15 2 1 GPIO Output Enabl...

Page 19: ...7 2 Reset Overview 770 17 2 1 Fundamental Reset 770 17 2 2 Software Reset 771 17 2 3 Secondary Bus Reset 771 17 2 4 PCI Reset 772 17 2 5 PCI Express Hot Reset 772 17 2 6 WARM_RST Reset Mechanism 772 1...

Page 20: ...d Registers 795 19 3 Accessing Peripheral Registers Using the Core Coprocessor Register Interface 795 19 4 Architecturally Reserved Memory Space 795 19 5 Default Memory Space Setup 796 19 6 Peripheral...

Page 21: ...apability 142 22 ATU Block Diagram 231 23 ATU Queue Architecture Block Diagram 232 24 Inbound Address Detection 238 25 Inbound Translation Example 239 26 4 Gbyte Section 0 of the Internal Bus Memory M...

Page 22: ...Enabled 649 79 DWORD Memory Read Protocol SMBus Block Write Block Read PEC Enabled 650 80 DWORD Configuration Read Protocol SMBus Word Write Word Read PEC Enabled 650 81 DWORD Configuration Read Proto...

Page 23: ...me Based Sampling Example 735 112 Block Diagram Waveforms of Time Based Sampling Example 736 113 Block Diagram Waveforms of Time Based Sampling Example 737 114 Block Diagram of HOQ Histogram Example 7...

Page 24: ...Reporting 134 24 PCI Bus Frequency Initialization 135 25 PCI X Initialization Pattern 136 26 Address Translation Unit Registers 143 27 ATU Internal Bus Memory Mapped Register Range Offsets 146 28 PCI...

Page 25: ...PCI X_Capability Identifier Register PCI X_Cap_ID 190 81 PCI X Next Item Pointer Register PCI X_Next_Item_Ptr 191 82 PCI X Command Register PCIXCMD 191 83 PCI X Status Register PCIXSR 193 84 ECC Contr...

Page 26: ...Queues 263 129 ATU Inbound Data Flow Ordering Rules 264 130 ATU Outbound Data Flow Ordering Rules 265 131 Inbound Transaction Ordering Summary 267 132 Outbound Transaction Ordering Summary 267 133 Par...

Page 27: ...D 335 187 VPD Next Item Pointer Register VPD_Next_Item_Ptr 335 188 VPD Address Register VPDAR 336 189 VPD Data Register VPDDR 336 190 PM_Capability Identifier Register PM_Cap_ID 337 191 PM Next Item P...

Page 28: ...r 2 OUMWTVR2 378 240 Outbound Upper Memory Window Base Address Register 3 OUMBAR3 379 241 Outbound Upper 32 bit Memory Window Translate Value Register 3 OUMWTVR3 380 242 Outbound Configuration Cycle A...

Page 29: ...er X MMCRx 440 297 Inbound MSI Interrupt Pending Registers IMIPR 0 3 441 298 SDMA Controller Unit Registers 446 299 LocalToHost Destination Lower Address Register L2H_DLAR 447 300 LocalToHost Destinat...

Page 30: ...ng Generation 529 348 SMCU Error Response 531 349 Memory Controller Register 535 350 SRAM Base Address Register SRAMBAR 536 351 SRAM Upper Base Address Register SRAMUBAR 536 352 SRAM ECC Control Regis...

Page 31: ...e Register 1 FINTSRC1 614 405 FIQ Interrupt Source Register 2 FINTSRC2 616 406 FIQ Interrupt Source Register 3 FINTSRC3 617 407 Interrupt Priority Register 0 IPR0 619 408 Interrupt Priority Register 1...

Page 32: ...Low Register UxDLL 685 460 UART x Divisor Latch High Register UxDLH 685 461 UART x FIFO Occupancy Register UxFOR 686 462 UART x Auto Baud Control Register UxABR 687 463 UART x Auto Baud Count Register...

Page 33: ...re Reset Control Bit Locations 773 513 Internal Bus Reset Control Bit Locations 775 514 Internal Bus Reset Summary 775 515 Reset Pin Summary 777 516 TPER Mode Per Function Storage Port Allocation CONT...

Page 34: ...05 001US 545 Intel 413808 and 413812 I O Controllers ATUE Configuration Space Base Address Offset 814 546 Address Translation Unit Registers ATUE 815 547 Intel 413808 and 413812 I O Controllers in TPE...

Page 35: ...8 and 413812 I O Controllers in TPER Mode October 2007 Developer s Manual Order Number 317805 001US 35 Contents Intel 413808 and 413812 Revision History Date Revision Description October 2007 001 Init...

Page 36: ...nsport firmware Using the term to describe a Usage Model simply means running intelligent RAID non host based typically simple levels such as 0 1 10 due to limited resources without burdening the I O...

Page 37: ...re as communicated by the SLI Configuration Port CONFIG_SLI_PORT command Complete details on the Application Core section of SRAM including alignment requirements addresses etc can be found in the SCD...

Page 38: ...tionally of course TPER firmware must be used for the 4138xx to operate in TPER mode see datasheet for complete listing of reset straps and their descriptions 4138xx mode CONTROLLER_ONLY 0 DF_SEL 2 0...

Page 39: ...listed in Table 2 Documentation References on page 40 SDMA SRAM DMA Engine Since there is no ADMA without DDR2 a separate DMA engine the SRAM DMA is provided to allow for the Application Core the abi...

Page 40: ...de Datasheet 317806a Intel 413808 and 413812 I O Controllers Datasheet 315040a Intel 413808 and 413812 I O Controllers in TPER Mode Design Guide 317807a Intel 413808 and 413812 I O Controllers Design...

Page 41: ...product described herein 1 3 1 How To Read This Document This document describes the product specific features of the 4138xx Each chapter describes a different feature and starts with an overview fol...

Page 42: ...two Intel XScale processors exclusive access to the north internal bus The 4138xx consolidates into a single system Two Intel XScale processors Eight Serial Attached SCSI Links also capable of suppor...

Page 43: ...I2 C Bus 72 Bit I F SAS Serial Bus Serial Bus Bridge Host Interface ATU One TDMA and One SDMA Multi Port SRAM Memory Controller Two UARTs Three I2 C Bus Interface APB PBI Unit Flash SAS 0 PHY SAS 1 P...

Page 44: ...O pins which are used for SAS Links for activity and status indicators Each SAS link uses two LSO pins The 81348 also supports two SGPIO busses The subsections that follow briefly overview each featur...

Page 45: ...oth the internal address and data busses on the south internal bus are parity protected on a byte wise basis 1 5 4 Application DMA Controller ADMA is not available in the 4138xx in any mode 1 5 5 Addr...

Page 46: ...n the 4138xx to be monitored 1 5 10 I2C Bus Interface Unit There are three I2C Inter Integrated Circuit Bus Interface Units that allow the Intel XScale processor to serve as a master and slave device...

Page 47: ...les framing Data bus cycles and provides the shared address and shared data paths from to units 1 5 14 Inter Processor Communication All intern processor communications on the 4138xx are over the inte...

Page 48: ...rrent value Writes to read only fields are treated as no op operations and does not change the current value nor result in an error condition A read clear field can also be read to return the current...

Page 49: ...he PCI signal name convention of using the symbol at the end of a signal name to indicate that the signal s active state occurs when it is at a low voltage The absence of the symbol indicates that the...

Page 50: ...s the ATU converts PCI addresses initiated by a PCI bus master to Internal Bus Addresses and initiates the data transfer on the 4138xx internal bus During outbound transactions the ATU converts intern...

Page 51: ...ication Revision 1 1 MSI capability as defined by PCI Local Bus Specification Revision 2 3 Hot Swap capability as defined by the Compact PCI Hot Swap Specification Revision 2 1 and PCI X capability as...

Page 52: ...2 Order Number 317805 001US Figure 4 ATU Queue Architecture Block Diagram P C I B u s I n t e r n a l B u s I n t e r f a c e P C I B u s I n t e r f a c e ADDRESS TRANSLATION UNIT I n t e r n a l B u...

Page 53: ...X commands supported for both inbound and outbound ATU transactions The type of operation seen by the ATU on inbound transactions is determined by the PCI master who initiates the transaction Claimin...

Page 54: ...t Acknowledge No No Reserved 0001 Special Cycle Special Cycle No No Reserved 0010 I O Read I O Read No1 Yes Reserved 0011 I O Write I O Write No1 Yes Reserved 0100 Reserved Reserved No No Reserved 010...

Page 55: ...n Reads are performed as split transactions Inbound memory write transactions have their addresses entered into the inbound write address queue IWADQ and data entered into the inbound write data queue...

Page 56: ...nslate Value Register 0 Inbound ATU Upper Translate Value Register 0 The ATU uses the following registers in inbound address window 1 translation Inbound ATU Base Address Register 1 Inbound ATU Limit...

Page 57: ...s in case of DACs is first bitwise ANDed with the bitwise inverse of the limit register This result is bitwise ORed with the ATU Translate Value which is then ORed with the 4 bit ATU Upper Translate V...

Page 58: ...0000H 8 Mbyte limit value Inbound Window Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH 8 Mbytes PCI_Address Value_Register B100 0000H Internal_Bus Address PCI Address Space I O Proce...

Page 59: ...ror is detected the uncorrectable attribute error mechanism described in Section 2 7 1 is used When an uncorrectable data error is detected while accepting data the slave interface sets the appropriat...

Page 60: ...and SERR may be asserted on the PCI interface The ATU initiator interface attempts a 128 bit wide transfer on the internal bus When the target that claims the request does not support 128 bit wide tr...

Page 61: ...eturn the data to the master on the PCI bus When there is a match and the data is not available a Retry is signaled with no other action taken When there is not a match and when the ITQ has less than...

Page 62: ...ternal bus is target aborted either a target abort or a disconnect with data is signaled to the initiator This is based on the ATU ECC Target Abort Enable bit bit 0 of the ATUIMR for ATU When set a ta...

Page 63: ...initiator interface performs an initiator completion in this case Also the completer reacquires the internal bus to deliver the remaining read data byte count to the ATU When operating in the convent...

Page 64: ...and P_IDSEL active where P_AD 1 0 are not 002 e g Type 1 commands During the configuration access address phase the PCI address is divided into a number of fields to determine the actual configuration...

Page 65: ...ed write split write in PCI X mode request cycle is latched into IDWQ and forwarded to the internal bus interface Once transaction ordering and priority have been satisfied the internal bus master int...

Page 66: ...conventional PCI mode The timer starts counting when the delayed request becomes a delayed completion by completing on the internal bus and all passing rules are satisfied When the originating master...

Page 67: ...med as split read operations Outbound transactions use a separate set of queues from inbound transactions Outbound write operations have their address entered into the outbound write address queue OWA...

Page 68: ...the ATU Configuration Register Outbound Enable bit as well as the Bus Master Enable bit in each function When the Outbound Enable bit is deasserted the internal bus outbound transaction master abort...

Page 69: ...138xx internal bus address space this removes the need for separate limit registers Figure 8 on page 69 illustrates the five outbound address translation windows Figure 8 Outbound Address Translation...

Page 70: ...w Table 5 Internal Bus to PCI Command Translation for Memory Windows Internal Bus Command Conventional PCI Command PCI X Command Writea a The internal bus request does not cross a QWORD address bounda...

Page 71: ...tion Cycle Address Register OCCAR See Section 2 14 for details on outbound translation register definition and programming constraints The translation algorithm used as stated is very similar to inbou...

Page 72: ...bus target interface stores write data into the OWQ until the internal bus transaction completes or the reaches a buffer boundary The initiator of the transaction is disconnected at an ADB when the tr...

Page 73: ...is claimed the PCI interface transfers data from the OWQ to the PCI bus until one of the following is true The PCI target signals a Retry or Single Data Phase Disconnect The ATU PCI initiator attempts...

Page 74: ...nerates a split completion transaction to return data to the internal bus requester When operating in the PCI X mode ATU may receive a split completion error message when attempting to read data on th...

Page 75: ...therefore is defined as 32 bit only Note the programming model uses the register interface for outbound configuration cycles from a hardware standpoint the address is entered into OTQ reads or OWADQ w...

Page 76: ...in order to set bits 27 24 properly 2 2 5 3 Outbound Configuration Cycle Error Conditions Master aborts during outbound configuration reads result in ATU aborting the read completion the on internal...

Page 77: ...PCI X Intel 413808 and 413812 2 2 6 Internal Bus Operation Complete internal bus operation of the 4138xx is defined in Chapter 7 0 System Controller SC and Internal Bus Bridge The ATU acts as both int...

Page 78: ...when using MSI X 2 3 1 Inbound Byte Swapping When enabled the swapping occurs as described in Figure 9 Inbound Byte Swapping for 32 bit PCI on page 78 and Figure 10 Inbound Byte Swapping for 64 bit P...

Page 79: ...rformed Note The byte swapping capability of the ADMA unit should be used to swap bytes within each DWORD for PCI to Memory Read Write DMA transfers Figure 11 Outbound Byte Swapping for Transaction wi...

Page 80: ...nal informs the system host that the configuration of the system has changed The system host then performs any necessary maintenance such as installing or quiesing a device driver HS_LSTAT 1 I Compact...

Page 81: ...y HS_FREQ 1 0 pins allow the 4138xx to determine the cPCI backplane operating frequency without needing to see a PCI X initialization pattern These pins are only valid when HS_SM is sampled as 0b duri...

Page 82: ...a 64 bit access by the assertion of ACK64 in response to a 64 bit request The Expansion ROM unit uses the ATU inbound transaction queue and the inbound read data queue When operating in the convention...

Page 83: ...n operating in the conventional PCI mode transactions The following rules apply to the PCI bus interface and govern the acceptance of data into IWQ and address into the tail of the IWADQ A memory writ...

Page 84: ...ial request cycle in both command and address Any data left in an IRQ after the delivery of a completion cycle on PCI is flushed This is possible since all internal bus memory is considered prefetchab...

Page 85: ...ating bus When operating in the PCI X mode a write completion message is generated by the ATU to indicate the successful execution of the configuration write transaction The IDWQ can only hold 32 bits...

Page 86: ...into the OTQ when not full and a split response termination is signaled to the requester on the internal bus Read data is fetched and returned to the requester on the internal bus 2 6 2 1 Relaxed Ord...

Page 87: ...nally strong ordering between outbound memory posted write requests and outbound non posted write requests are not maintained as indicated in Table 14 on page 88 For best performance the user should d...

Page 88: ...PCI bus Outbound Read Request SRR The address command of a split read cycle initiated on the internal bus The read data is returned in the Outbound Read Completion cycle Inbound Read Completion DRC P...

Page 89: ...st complete on the internal bus before Transaction B since an outbound read completion can not pass an inbound write Also Transaction A must complete before Transaction C since an inbound write can no...

Page 90: ...e in IWQ Is there an Inbound Write Request with an earlier time stamp Yes Do Not Assign Token Allow previous Transaction to Complete No Assign Token Inbound Read Request in ITQ Is there an Inbound Wri...

Page 91: ...Write Completion in IRQ Is there an Outbound Posted Write with an earlier time stamp Yes Do Not Assign Token Allow previous Transaction to Complete No Assign Token Is there an Inbound Read Completion...

Page 92: ...curs on the internal bus interface the same data issues on the PCI bus with either bad parity or uncorrectable ECC error For inbound transactions the bad parity or uncorrectable ECC errors results in...

Page 93: ...rity is good done else error create an error log Interrupt the core if enabled On an outbound write request data parity is checked on the data bus D 127 0 The parity bits are checked by first bit XORi...

Page 94: ...eres to the error conditions defined within the PCI specification for both requester and target operation Error conditions on the internal bus are caused by an ECC error from the Memory Controller see...

Page 95: ...actions is taken Set the SERR Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no action When the ATU SE...

Page 96: ...erforms the following actions based on the constraints specified The error is corrected and the ATU completes the transaction on the PCI bus as when no error had occurred Then the transaction is forwa...

Page 97: ...and uncorrectable data errors occurring at the target for outbound writes However there is no error response for uncorrectable data errors on inbound configuration write completion messages and inboun...

Page 98: ...R When set no action When the ATU is operating in the PCI X mode the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the PCIXCMD register is clear assert SE...

Page 99: ...I Master Parity Error bit in the ATUISR When set no action When the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the PCIXCMD register is clear assert SER...

Page 100: ...t the SERR Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no action When the ATU SERR Detected Interrup...

Page 101: ...and no error bits are set 2 7 3 5 2 Split Response Termination As a target the ATU may encounter this error when operating in the PCI X mode Inbound read uncorrectable data errors occur during the Spl...

Page 102: ...t in the ATUIMR is clear set the PCI Master Parity Error bit in the ATUISR When set no action When the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the P...

Page 103: ...y Error bit in the ATUSR is set When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear set the PCI Master Parity Error bit in the ATUISR When set no action When the SERR Enable...

Page 104: ...is cleared the ATU retries the transaction by asserting STOP and enqueues the Delayed Write Request cycle to be forwarded to the internal bus PERR is not asserted The Detected Parity Error bit in the...

Page 105: ...s are taken An Uncorrectable Split Write Data Error message with message class 2h completer error and message index 01h Uncorrectable Split Write Data Error is initiated by the ATU on the PCI bus that...

Page 106: ...s SERR additional actions are taken Set the SERR Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no acti...

Page 107: ...However the ATU provides no error response for correctable data errors on inbound read requests In general when the ATU is receiving data from the PCI bus as a target any correctable data errors are c...

Page 108: ...taken The error is corrected and the ATU completes the transaction on the PCI bus as when no error had occurred Then the transaction is forwarded to the internal bus normally Update the ECC Control a...

Page 109: ...ex 00h Master Abort The following actions with given constraints are performed by ATU when a master abort is detected by the PCI initiator interface or the PCI target interface receives a Master Abort...

Page 110: ...etion Message the ATU discards the Split Completion and take no further action 2 7 5 3 Master Aborts Signaled by the ATU as a Target 2 7 5 3 1 Uncorrectable Address Errors The ATU can only signal this...

Page 111: ...lit Completion Error Message class 1h bridge error and index 01h Target Abort The following actions with the given constraints are performed by the ATU when a target abort is detected by the PCI initi...

Page 112: ...r Abort on the Internal Bus on page 115 for details on the ATU response to an Internal Bus Master Abort 2 7 6 3 2 Internal Bus Target Abort A target abort can be signaled by the ATU during an inbound...

Page 113: ...he OTQ Conversely the ATU does not assert DEVSEL for any split completion transaction where either the Requester ID does not match that of the ATU or the Tag does not match that of any currently outst...

Page 114: ...Assertion bit in the ATUCR has been set and the SERR Enable bit is set in the ATUCMD Note that the SERR manual assertion bits must be cleared manually before they can be set again resulting in SERR as...

Page 115: ...with the given constraints are performed by the ATU when a master abort is detected by the internal master interface during an inbound write request transaction Set the Internal Bus Master Abort bit...

Page 116: ...ar set the PCI Target Abort target bit in the ATUISR When set no action Flush the transaction that was master aborted from the ITQ after the target abort is delivered on the PCI interface When operati...

Page 117: ...s cleared in the ATUIMR a disconnect with data is returned to the PCI initiator during the data word that was target aborted on the internal bus In both cases the IRQ is flushed after the completion c...

Page 118: ...detected a parity error on the PCI interface Inbound write parity error will be detected and logged by the internal bus target For write data that has to flow through the internal bus bridge the bridg...

Page 119: ...then signal SERR In PCI X Mode claim the transaction and complete as when no error had occurred and signal SERR upon uncorrectable error detection All SERR Asserted bit 14 SERR Asserted bit 10 ATUIMR...

Page 120: ...X Signal SERR PCI X Master Parity Error bit 8 Master Parity Error bit 0 ATUIMR bit 2 PCI X SERR Asserted bit 14 SERR Asserted bit 10 ATUIMR bit 6 PCI X N A SERR Detected bit 4 ATUCR bit 9 PCI X Receiv...

Page 121: ...able Data Error PCI X None Inbound Configuration Write Completion Message Correctable Data Error PCI X None Inbound Read Request Correctable Data Error PCI X2 None Inbound Write Request Correctable Da...

Page 122: ...ound Read Completions Master Abort PCI X None Inbound Configuration Write Completion Message Master Abort PCI X None Outbound Read Request Target Abort All None All Target Abort master bit 12 PCI Targ...

Page 123: ...Parity Error Response bit 6 of the ATUCMD register is set c Table assumes that Data Parity Recovery Enable bit 0 of the PCIXCMD is clear d When a correctable or uncorrectable data error occurs in PCI...

Page 124: ...CI Target Abort target bit 1 ATUIMR bit 3 PCI X N A Initiated Split Completion Error Message bit 13 ATUIMR bit 10 Inbound Read Request Target Abort All In the Conventional Mode signal Target Abort In...

Page 125: ...s the MSI capability structure The capability structure includes the Section 4 7 20 MSI Capability Identifier Register Cap_ID on page 429 the Section 4 7 21 MSI Next Item Pointer Register MSI_Next_Ptr...

Page 126: ...ollers in TPER Mode Developer s Manual October 2007 126 Order Number 317805 001US 2 9 Internal Interrupts The ATU has 3 internal interrupts that connect to the internal Interrupt Controller Unit ATU I...

Page 127: ...finitions of compliant VPD format 2 10 1 Configuring Vital Product Data Operation By default the 4138xx VPD functionality is not configured for operation Specifically the VPD Extended Capabilities Lis...

Page 128: ...VPDAR 14 0 Four bytes are always transferred between this register and the VPD storage component 2 10 2 1 Reading Vital Product Data Using the fields defined in the VPD Capabilities List Item the 413...

Page 129: ...XScale processor is triggered and bit 17 of the ATUISR is set Meanwhile the host processor polls the VPDAR register waiting for the Flag to be cleared Warning When any configuration writes to either t...

Page 130: ...t MWI Enable is globally enabled when only one of the functions enables MWI Enable Bit 2 Bus Master Enable Each function can independently control this bit Bit 1 Memory Enable Each function can indepe...

Page 131: ...parity error is reported to only the function involved Bit 14 SERR Asserted SERR Asserted is reported to only the function involved Bit 13 Master Abort Master Abort is reported to only the function in...

Page 132: ...modes of operation 2 12 3 PCI Reset P_RSTOUT When the Central Resource is enabled PCIX_EP 1 the ATU controls generation of P_RSTOUT for the PCI Bus segment attached to the ATU The ATU controls the PCI...

Page 133: ...cks To facilitate the use of an external driver the CR_FREQ 1 0 pins are driven based on the settings in the PCI X capability field bits 19 16 in the PCI Configuration and Status Register PCSR These o...

Page 134: ...mber of slots is necessary When for example a 133 MHz PCI X capable adapter was the sole occupant of a two slot segment then it would be necessary to slow the bus to 100 MHz even though the card repor...

Page 135: ...ot secondary bus the PCIXM1_100 pull down strapping ensures that the bus runs at no greater than 100 MHz in PCI X mode regardless of the reported downstream device capabilities When a card is plugged...

Page 136: ...t PCIX_EP 0 PCSR 19 16 contains the initialization pattern captured off the bus during P_RST Table 25 PCI X Initialization Pattern PERR DEVSEL STOP TRDY Modea a 4138xx supports neither PCI X 533 Mode...

Page 137: ...r 317805 001US 137 Address Translation Unit PCI X Intel 413808 and 413812 When operating as an endpoint in Hot Swap mode HS_SM 0 PCSR 19 16 is set based on the HS_FREQ 1 0 pins For more details see Ta...

Page 138: ...413812 Address Translation Unit PCI X Intel 413808 and 413812 I O Controllers in TPER Mode Developer s Manual October 2007 138 Order Number 317805 001US 2 13 Embedded Bridge Functionality Note Not sup...

Page 139: ...ation on page 64 ATU configuration space is function number zero of the 4138xx single function PCI device Beyond the required 64 byte header format ATU configuration space implements extended register...

Page 140: ...eaders supported in the ATUs configuration space To enable the PCI Bus Power Management Interface Specification Revision 1 1 compliance support the Power State Transition interrupt mask in bit 8 of th...

Page 141: ...apabilities Headers supported in the ATUs configuration space The first byte at the Extended Configuration Offset D0H is the PCI X Capability Identifier Register Section 2 14 53 This identifies this E...

Page 142: ...Item Pointer Register is set to 00H indicating that there are no additional Extended Capabilities Headers supported in the ATUs configuration space The following sections describe the ATU and Expansio...

Page 143: ...4 ATU Device ID Register ATUDID on page 147 004H Section 2 14 5 ATU Command Register ATUCMD on page 148 006H Section 2 14 6 ATU Status Register ATUSR on page 149 008H Section 2 14 7 ATU Revision ID R...

Page 144: ...m Pointer Register PM_Next_Item_Ptr on page 187 09AH Section 2 14 50 ATU Power Management Capabilities Register APMCR on page 188 09CH Section 2 14 51 ATU Power Management Control Status Register APMC...

Page 145: ...ction 2 14 74 Outbound Upper 32 bit Memory Window Translate Value Register 1 OUMWTVR1 on page 213 318H Section 2 14 75 Outbound Upper Memory Window Base Address Register 2 OUMBAR2 on page 214 31CH Sec...

Page 146: ...easserted 1 Asserted 0 4 C000H Deasserted 1 Deasserted 1 4 D000H Table 28 PCI X Pad Registers Register Offset Section Register Name Acronym Page 2100H Section 2 14 88 PCIX RCOMP Control Register PRCR...

Page 147: ...r ID to simulate the interface of a standard mechanism currently used by existing application software PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro r...

Page 148: ...te registers but in all other respects treats the transaction as though it had no error Correctable ECC errors are corrected independent of the state of this bit 05 02 VGA Palette Snoop Enable The ATU...

Page 149: ...X mode 11 02 Target Abort target set when the ATU interface acting as a target terminates the transaction on the PCI bus with a target abort 10 09 012 DEVSEL Timing These bits are read only and defin...

Page 150: ...bit is a 1 are any of the 4138xx s INT A D signals asserted by the ATU function Note Setting the Interrupt Disable bit to a 1 in bit 10 of ATUCMD has no effect on the state of this bit 02 00 0002 Rese...

Page 151: ...cessor Specification Update ATU Revision identifies the revision number PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro Attribute Legend RV Reserved PR Preserved RS...

Page 152: ...Ds Cacheline size is restricted to either 0 8 or 16 DWORDs PCI IOP Attributes Attributes 7 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Attribute Legend RV Reserved PR Preserved RS Read Set RW...

Page 153: ...e Function Multi Function Device Identifies the 4138xx as a single function or multi function PCI device depending on the setting of the DF_SEL 2 0 strap during P_RST assertion Note The 4138xx can be...

Page 154: ...bit is set Setting this bit generates an interrupt to the Intel XScale processor to perform a software BIST function The Intel XScale processor clears this bit when the BIST software has completed wi...

Page 155: ...le Indicator and the Type Indicator Assuming IALR0 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is clea...

Page 156: ...of IABAR0 is set to indicate 32 bit addressability the IAUBAR0 register attributes are read only Prior to changing the Type Indicator in the IABAR0 to support 32 bit addressability the IAUBAR0 must b...

Page 157: ...Assuming IALR1 is not cleared c Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the...

Page 158: ...R1 is set to indicate 32 bit addressability the IAUBAR1 register attributes are read only By default the IAUBAR1 register has read only attributes Prior to changing the Type Indicator in the IABAR1 to...

Page 159: ...ared e Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the user should also set the...

Page 160: ...tor of IABAR2 is set to indicate 32 bit addressability the IAUBAR2 register attributes are read only By default the IAUBAR2 register has read only attributes Prior to changing the Type Indicator in th...

Page 161: ...This register uniquely identifies the add in board or subsystem vendor PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw...

Page 162: ...configuration allows the ERBAR to be programmed per PCI Local Bus Specification Revision 2 3 The Expansion ROM Base Address Register s programmed value must comply with the PCI programming requiremen...

Page 163: ...first Capability list In the case of the 4138xx this is the PCI Bus Power Management extended capability as defined by the PCI Bus Power Management Interface Specification Revision 1 1 Table 48 ATU C...

Page 164: ...08H Bit zero is a zero so the device requires memory address space Bit three is one so the memory does supports prefetching Scanning upwards starting at bit four bit twenty is the first one bit found...

Page 165: ...r DACs Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus Inbound ATU Upper Base Address Register 2 N A Together with ATU Base A...

Page 166: ...16 10H through 254 FEH are reserved 255 FFH indicates unknown or no connection The operating system or device driver can examine each device s interrupt pin and interrupt line register to determine wh...

Page 167: ...how often a bus master typically requires access to the PCI bus and the duration of a typical transfer when it does acquire the bus This information is useful in determining the values to be programme...

Page 168: ...master typically requires access to the PCI bus and the duration of a typical transfer when it does acquire the bus This information is useful in determining the values to be programmed into the bus m...

Page 169: ...of 0 in a bit within the IALR0 makes the corresponding bit within the IABAR0 a read only bit which always returns 0 A value of 1 in a bit within the IALR0 makes the corresponding bit within the IABAR...

Page 170: ...zes for Base Address Registers on page 164 The default address allows the ATU to access the internal 4138xx memory mapped registers 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the AT...

Page 171: ...a one to one correspondence A value of 0 in a bit within the IALR1 makes the corresponding bit within the IABAR1 a read only bit which always returns 0 A value of 1 in a bit within the IALR1 makes th...

Page 172: ...ned with the IABAR1 register s programmed value see Section 2 14 23 Determining Block Sizes for Base Address Registers on page 164 11 01 000H Reserved 00 0 Big Endian Byte Swap enable 0 No swap perfor...

Page 173: ...r bits 31 to 12 with a one to one correspondence A value of 0 in a bit within the IALR2 makes the corresponding bit within the IABAR2 a read only bit which always returns 0 A value of 1 in a bit withi...

Page 174: ...register s programmed value see Section 2 14 23 Determining Block Sizes for Base Address Registers on page 164 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte swa...

Page 175: ...it which always returns 0 A value of 1 in a bit within the ERLR makes the corresponding bit within the ERBAR read write from PCI Table 64 Expansion ROM Limit Register ERLR Bit Default Description 31 1...

Page 176: ...BAR register s programmed value see Section 2 14 23 Determining Block Sizes for Base Address Registers on page 164 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte...

Page 177: ...clear the Intel XScale processor is not interrupted when P_SERR is detected 08 02 Halt ATU On Error Enable When set and a Data Parity Master Abort or Target Abort error occurs on an Outbound PCI Writ...

Page 178: ...or 66 MHz Use P_M66EN to determine frequency 10 PCI X Mode 66 MHz 01 PCI X Mode 100 MHz 00 PCI X Mode 133 MHz Note 4138xx does not support CompactPCI Hot Swap in PCI X Mode2 25 PCIX_EP PCIX End Point...

Page 179: ...value on the PCI bus As a Central Resource this field controls the initialization pattern driven on the PCI bus during reset and the value driven on the CR_FREQ 1 0 pins The default value of this fiel...

Page 180: ...before the timer expired Note When the firmware timer is disabled firmware is responsible to clear the Configuration Request Retry bit Otherwise the ATU indefinitely retries all host configuration cyc...

Page 181: ...Interrupt 14 02 Detected Correctable Error This bit is set in PCI X Mode 2 only when the 4138xx detects a single bit ECC error in any phase of a PCI transaction 13 02 Initiated Split Completion Error...

Page 182: ...I bus with a target abort 00 02 PCI Master Parity Error Master Parity Error The ATU interface sets this bit under the following conditions The ATU asserted PERR itself or the ATU observed PERR asserte...

Page 183: ...s setting of bit 14 of the ATUISR and generation of the Correctable Error interrupt when in PCI X Mode 2 a correctable error is detected in any phase of a PCI transaction 0 Not Masked 1 Masked 10 02 I...

Page 184: ...f the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set 0 Not Masked 1 Masked 01 02 ATU Inbound Error SERR Enable Controls when ATU asserts when enabled through the ATU...

Page 185: ...ility list and hence this register is set to 00H Table 71 VPD Capability Identifier Register VPD_Cap_ID Bit Default Description 07 00 03H Cap_Id This field with its 03H value identifies this item in t...

Page 186: ...nt has completed Please see Section 2 10 Vital Product Data on page 127 for more details on how the 4138xx handles the data transfer 14 0 0000H VPD Address This register is written to set the DWORD al...

Page 187: ...bility list is located at off set B0H Note that the PM_Next_Item_Ptr can be written by the processor Table 75 PM_Capability Identifier Register PM_Cap_ID Bit Default Description 07 00 01H Cap_Id This...

Page 188: ...nt State 9 12 D1_Support This bit is set to 12 indicating that the 4138xx supports the D1 Power Management State 8 6 0002 Aux_Current This field is set to 0002 indicating that the 4138xx has no curren...

Page 189: ...le of asserting the PME signal in any state since PME is not supported by the 4138xx 14 9 00H Reserved 8 02 PME_En This bit is hard wired to read only 02 since this function does not support PME gener...

Page 190: ...r ATUSPR Bit Default Description 31 0 0000H Scratch Pad Data Entire register is available for application specific purposes PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw r...

Page 191: ...xx is the CompactPCI extended capabilities header PCI IOP Attributes Attributes 7 4 0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Writ...

Page 192: ...4 2 2048 3 4096 1 12 Enable Relaxed Ordering When set the 4138xx may set the relaxed ordering bit in the Requester Attributes of Transactions 0 02 Uncorrectable Data Error Recovery Enable The device d...

Page 193: ...ected Split Completion with this device s Requester ID is received Once set this bit remains set until software writes a 1 to this location 0 no unexpected Split Completion has been received 1 an unex...

Page 194: ...system hardware The system must assign a device number other than 00h 00h is reserved for the source bridge The function uses this number as part of its Requester ID and Completer ID Each time the fun...

Page 195: ...are treated as uncorrectable errors including the setting of status bits and assertion of error indicator signals on the bus Disabling single bit error correction enhances the error detection capabil...

Page 196: ...x is enabled to latch information about an ECC error When the 4138xx detects an error it latches the phase of the error in this register and stores status information for the error in this register an...

Page 197: ...ditional correctable ECC error has been detected 1 One or more additional correctable ECC errors have been detected 1 0 002 Reserved Table 84 ECC Control and Status Register ECCCSR Sheet 3 of 3 Bit De...

Page 198: ...Note The ECC Control and Status Register ECCCSR ECC First Address Register ECCFAR ECC Second Address Register ECCSAR and ECC Attribute Register ECCAR report the actual transaction that has the error...

Page 199: ...Control and Status Register ECCCSR ECC First Address Register ECCFAR ECC Second Address Register ECCSAR and ECC Attribute Register ECCAR report the actual transaction that has the error For example wh...

Page 200: ...had an error the information regarding the Split Completion is reported 2 14 61 CompactPCI Hot Swap Capability ID Register The following register block provides support of CompactPCI Hot Swap functio...

Page 201: ...sertion to Retry Type 0 configuration cycles bit 2 of PCSR Typically the Intel XScale processor would be enabled to boot immediately following P_RST assertion in this case bit 1 of PCSR as well Please...

Page 202: ...to it 4138xx de asserts P_ENUM when currently asserted and is then armed for a possible future extraction event EXT bit assertion is enabled 06 0b EXT Pending EXTraction of board 4138xx sets this bit...

Page 203: ...of the INS or EXT bits of this register When 1b 4138xx does not assert P_ENUM under any circumstances 00 0b DHA Device Hiding Armed When 1b When HS_SM 0b and LSTAT 1b Switch open and the LOO bit 1b 4...

Page 204: ...Type Indicator for 64 bit addressability This is the default for IABAR3 Assuming a non zero value is written to IALR3 the user may set the Prefetchable Indicator or the Type Indicator a Since non pre...

Page 205: ...ate 32 bit addressability the IAUBAR3 register attributes are read only By default the IAUBAR3 register has read only attributes Prior to changing the Type Indicator in the IABAR3 to support 32 bit ad...

Page 206: ...al Bus Specification Revision 2 3 for additional information on programming base address registers Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register bits 31 to 12 with a one t...

Page 207: ...IABAR3 register s programmed value see Section 2 14 23 Determining Block Sizes for Base Address Registers on page 164 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a...

Page 208: ...16 is set to 0000H see I O Transactions on page 71 Table 96 Outbound I O Base Address Register OIOBAR Bit Default Description 31 12 0 FFFBH Outbound I O Base Address This value represents bits 35 to 1...

Page 209: ...ess Register OIOBAR with the a fixed length of 64 Kbytes Table 97 Outbound I O Window Translate Value Register OIOWTVR Bit Default Description 31 16 0000H Outbound I O Window Translate Value Used to c...

Page 210: ...5 32 matches OUMBAR0 3 0 30 28 0002 Outbound Window 0 Function Number Mapping Errors with Outbound Memory Window 0 transactions PCI or Internal Bus is associated with the function number contained in...

Page 211: ...t address space When this register is all zero then a SAC is generated on the PCI bus Table 99 Outbound Upper 32 bit Memory Window Translate Value Register 0 OUMWTVR0 Bit Default Description 31 00 000...

Page 212: ...A 35 32 matches OUMBAR1 3 0 30 28 0002 Outbound Window 1 Function Number Mapping Errors with Outbound Memory Window 1 transactions PCI or Internal Bus is associated with the function number contained...

Page 213: ...t address space When this register is all zero then a SAC is generated on the PCI bus Table 101 Outbound Upper 32 bit Memory Window Translate Value Register 1 OUMWTVR1 Bit Default Description 31 00 00...

Page 214: ...5 32 matches OUMBAR2 3 0 30 28 0002 Outbound Window 2 Function Number Mapping Errors with Outbound Memory Window 2 transactions PCI or Internal Bus is associated with the function number contained in...

Page 215: ...ddress space When this register is all zero then a SAC is generated on the PCI bus Table 103 Outbound Upper 32 bit Memory Window Translate Value Register 2 OUMWTVR2 Bit Default Description 31 00 0000...

Page 216: ...A 35 32 matches OUMBAR3 3 0 30 28 0002 Outbound Window 3 Function Number Mapping Errors with Outbound Memory Window 3 transactions PCI or Internal Bus is associated with the function number contained...

Page 217: ...t address space When this register is all zero then a SAC is generated on the PCI bus Table 105 Outbound Upper 32 bit Memory Window Translate Value Register 3 OUMWTVR3 Bit Default Description 31 00 00...

Page 218: ...initiate a Type 0 configuration cycle the OCCAR should always be loaded based on the PCI X definition for the Type 0 configuration cycle address When operating in Conventional mode the 4138xx clears...

Page 219: ...rmine where errors get logged For 4138xx the function number should be 0 for endpoint usage and match the ATUX function number readable in PCI X Status Register PCIXSR for Root Complex modes Table 107...

Page 220: ...e error when PCIECSR bit 0 is set 0000 Address Parity Error 0001 Data Parity Error 0010 Master Abort 0011 Target Abort 0100 Received Split Completion Error Message 0101 Unexpected Split Completion 011...

Page 221: ...tions on page 94 Note The PCI Interface Error Control and Status Register PIECSR PCI Interface Error Address Register PCIEAR and PCI Interface Error Upper Address Register PCIEUAR report the original...

Page 222: ...r Control and Status Register PIECSR PCI Interface Error Address Register PCIEAR and PCI Interface Error Upper Address Register PCIEUAR report the original transaction when an error is detected on the...

Page 223: ...had the error by reading this register and decoding the contents of the PCIECSR For error details see Section 2 7 ATU Error Conditions on page 94 Table 112 PCI Interface Error Context Address Registe...

Page 224: ...last PCI agent using the bus 1 Bus is always parked on 4138xx 07 02 Reserved 06 02 ATU Ring Allocation Priority ring allocation for 4138xx ATU requests 0 The ATU is in the low priority ring of the in...

Page 225: ...CI clocks allotted to the current agent after which the arbiter grants another agent that is requesting the bus Table 114 Multi Transaction Timer MTT Bit Default Description 07 03 00H Timer Count Valu...

Page 226: ...ce Voltage 2 b01 5 Reference 2 b10 5 Reference 08 07 012 Drive strength select for ODT RCOMP pad 2 b00 103 0 ohms 2 b01 110 0 ohms 2 b10 120 0 ohms 06 04 0102 Drive strength select for RCOMP pad dedic...

Page 227: ...Manual Override Values Registers PPODSMOVR Bit Default Description 31 14 00000H Reserved 13 08 1000002 N ODT drive strength manual override values for PCIX pad 07 06 002 Reserved 05 00 1000002 P ODT...

Page 228: ...1 5 Bit Default Description 31 28 0H Reserved 27 24 10002 N slew rate manual override values for PCIX pad 23 20 00002 Reserved 19 16 10002 P slew rate manual override values for PCIX pad 15 14 002 Res...

Page 229: ...t Default Description 31 28 0H Reserved 27 24 10002 N slew rate manual override values for PCIX pad 23 20 00002 Reserved 19 16 10002 P slew rate manual override values for PCIX pad 15 14 002 Reserved...

Page 230: ...ultiple inbound or outbound transactions and processes them simultaneously During inbound transactions the ATU converts PCI addresses initiated by a PCI Express Requester to internal bus addresses and...

Page 231: ...Revision 1 0a Additionally the ATU includes three PCI Express Extended capability headers that implement Advanced Error Handling Device Serial Number and Power Budgeting as defined in the PCI Express...

Page 232: ...IPHQ 16Entries Inbound Non Posted Header INPHQ 8Entries Outbound Posted Data Queue OPDQ 4KBytes Outbound Completion Data Queue OCPLDQ 4KBytes Outbound Completion Header Queue OCPLHQ 8Entries Outbound...

Page 233: ...polarity should enable straight routing between the component and the PCI Express card edge connector The lane reversal feature can be utilized to simplify applications where this component is connec...

Page 234: ...ains pending until one of the earlier active transactions is completed Each active outbound read request may be fragmented into sub requests based on the MAX_READ_REQUEST_SIZE parameter programmed in...

Page 235: ...ound transactions generated by the core processor is determined by the internal bus address and the fixed outbound windowing scheme ATU supports all four address spaces defined within the PCI Express...

Page 236: ...00 Yes Yes Read MRdLk 00 01 0 0001 Unsupported Request No N A MWr 10 11 0 0000 Yes Yes Write IORd 00 0 0010 Yes Yes Read IOWr 10 0 0010 Yes Yes Write CfgRd0 00 0 0100 Yes Yes Read CfgWr0 10 0 0100 Yes...

Page 237: ...NPQ is capable of holding up to 8 non posted requests and any associated data Operation of the internal bus is defined in Section 7 0 System Controller SC and Internal Bus Bridge PCI Express has three...

Page 238: ...ers the upper 32 bits of the address is assumed to be 0000_0000h during address comparison The algorithm for detection is Figure 24 shows an example of inbound address detection The lower 32 bits of t...

Page 239: ...ation ID Routed on page 242 Figure 25 shows an inbound translation example for 32 bit addressing This example would hold true for an inbound transaction from PCI Express Link Equation 9 Inbound Transl...

Page 240: ...bus when IPHQ has at least one entry When the internal bus is granted the internal bus master interface initiates the write transaction by driving the translated address onto the internal bus For deta...

Page 241: ...Outbound Completion Data Queue A zero length read memory read request of 1 DW with no bytes enabled has no side effects Once a completion transaction has started it continues until one of the followi...

Page 242: ...cle Translation ID Routed The 4138xx ATU only accepts Type 0 configuration requests with a function number of zero when bit 7 of the ATUHTR see Section 3 17 11 ATU Header Type Register ATUHTR on page...

Page 243: ...cleared then when a second vendor specific message transaction reaches the head of the IPHQ it stalls until the message registers are freed by clearing the Message Received bit in the ATUISR Since mes...

Page 244: ...nd get data returned into the Inbound Completion Data Queue ICPLDQ Refer to Section 3 8 2 for details of outbound queue architecture Outbound configuration transactions use a special outbound port str...

Page 245: ...ively of the 64 Gbyte Internal Bus address space The response of the ATU to Outbound Transactions is globally controlled by the Outbound Enable bit in the ATU Configuration Register as well as the Bus...

Page 246: ...equal to 01H Outbound Upper Memory Base Address Register 1 OUMBAR1 Default Value equal to 02H Outbound Upper Memory Base Address Register 2 OUMBAR2 Default Value equal to 03H Outbound Upper Memory Bas...

Page 247: ...PCI Express Intel 413808 and 413812 Figure 26 4 Gbyte Section 0 of the Internal Bus Memory Map Peripheral Memory Mapped Registers 0 0000 0000H ADDRESS Address Space Used for Other Resources Code Data...

Page 248: ...Configuration Cycle Address Register OCCAR See Section 3 17 for details on outbound translation register definition and programming constraints The translation algorithm used as stated is very simila...

Page 249: ...Outbound I O Cycle Translation Window default 1 0000 0000H 2 0000 0000H 0 0000 0000H 1 FFFF FFFFH 2 FFFF FFFFH Memory Window 0 Memory Window 1 Code Data I O Window 4 Gbytes 64 Kbytes External Memory...

Page 250: ...evice and the ATU associates each transaction with the correct PCI Express function number according to the following algorithm Outbound Configuration transactions use the function number field specif...

Page 251: ...s enabled for transmission on the PCI Express Link The PCI interface is responsible for completing the outbound write transaction with the PCI address translated from the OPHQ and the data in the OPDQ...

Page 252: ...the head of the ONPQ has at least one entry and the ordering rules are satisfied Once the request is issued the Transaction Pending bit is set in the PCI Express Device Status Register PE_DSTS When a...

Page 253: ...transaction with the address in the associated address register When the data register is accessed the address is pulled from the Outbound Configuration Cycle Address Register OCCAR to generate the TL...

Page 254: ...ernal bus cycles 1 Write outbound message transaction header registers 0 3 2 Write the data to the outbound message transaction payload register This write causes the generation of the message TLP on...

Page 255: ...Outbound Upper Memory BAR 0 3 OUMBAR0 3 Note The Messaging Unit MU Memory is mapped in PCI Window 0 ATU Base Address Register 0 along with the MSI X table structures Byte swapping should not be enable...

Page 256: ...wap bytes within each DWORD for PCI to Memory Read Write DMA transfers Figure 29 Outbound Byte Swapping for Transaction with Byte Count of 1 Figure 30 Outbound Byte Swapping for Transactions with Byte...

Page 257: ...fer data between the PCI system and the 4138xx and notifies the respective system when new data arrives The MU is located on the south internal bus of the 4138xx and is accessed via the ATU The MU is...

Page 258: ...ow power state from an End Point or Upstream Port RC PME_Turn_Offa Notification of pending turn off of link clock and power RC Generated from PEMCSR PM_PMEb PME message conveying the ID of the PME ori...

Page 259: ...bilities register and interrupt the core Vendor Defined Message Type 0 1 Vendor Specific Message It is used by devices to communicate with SRL device core RC End Point Log in Inbound Vendor Message Re...

Page 260: ...he associated device The code can be discarded once executed Expansion ROM registers are described in Section 3 17 22 The inbound ATU supports an inbound Expansion ROM window which works like the inbo...

Page 261: ...rnal bus The corresponding header queue IPHQ is capable of holding 8 entries The following rules apply to the PCI Express Link interface and govern the acceptance of data into inbound posted queues Po...

Page 262: ...Completion Queue Structure The inbound completion queue provides insures space for all outstanding outbound read requests This queue is 4KB in size and is used to order the completion data before retu...

Page 263: ...ter abort or target abort cases For outbound reads the address is entered into the OTQ when not full and a split response termination is signaled to the requester on the internal bus Read data is fetc...

Page 264: ...ed write requests are not maintained as indicated in Table 130 on page 265 For best performance the user should designate the two Outbound Memory Windows as non cachable and bufferable from theIntel X...

Page 265: ...perations multiple transactions may exist within the IPHQ and the corresponding IPDQ at any point in time The ordering of these transactions is based on a time stamp basis Transactions entering the qu...

Page 266: ...IWQ The two transactions at the head of the queues moving data in an inbound direction are now Transaction C an inbound write and Transaction B an outbound read completion Ordering states that an inbo...

Page 267: ...amp Yes Do Not Assign Token Allow previous Transaction to Complete No Assign Token Inbound Completion in ICPLHQ Is the relaxed order bit set in the header and the Enable Relaxed Ordering bit set in th...

Page 268: ...orrupt For an inbound write request the ATU computes and appends address parity and data parity before placing the TLP in the inbound queues When an ECRC violation is detected the packet is treated as...

Page 269: ...parity is good done else error create an error log Interrupt the core if enabled On an outbound request with data data parity is checked on the data bus D 127 0 The parity bits are checked by first bi...

Page 270: ...e of the ATU and have different effects depending on the error Error conditions and their effects are described in the following sections PCI Express error conditions and the action taken on the link...

Page 271: ...sactions are still logged and reported by the target device Note When the severity for the error is programmed to fatal in the PCI Express Uncorrectable Error Severity ERRUNC_SEV register then it is n...

Page 272: ...a 4K boundary When 4138xx is operating as Endpoint and ATUE receives Assert_INTx Deassert_INTx messages Assert_INTx Deassert_INTx messages do not use default Traffic Class TC0 Power Management messag...

Page 273: ...the requestor Note When the severity setting in PCI Express Uncorrectable Error Severity ERRUNC_SEV register is fatal this is not an Advisory Error and an ERR_FATAL is sent to the root complex 3 9 1 5...

Page 274: ...tempt to get valid data When firmware decides to stop retrying the transaction it must escalate the error by setting the Generate ERR_NONFATAL bit in the PCI Express Advisory Error Control Register PI...

Page 275: ...internal bus errors The tables assume that all error reporting is enabled through the appropriate command registers unless otherwise noted Example A poisoned TLP is received Depending on the setting...

Page 276: ...E_DLOG ATUSR 14 PE_DSTS 3 PE_DSTS 2 or 1 ERRUNC_STS 20 PIE_STS 20 ATUISR 10 8 ATUCMD 8 PE_DCTL 2 or 1 ATUIMR 8 ERRUNC_MSK 20 PIE_MSK 20 Completion Timeout Requester Send ERR_FATAL ERR_NON FATAL to Roo...

Page 277: ...nd ERR_COR to Root Complex PE_DSTS 0 ERRCOR_STS 12 ATUISR 9 PE_DCTL 0 ERRCOR_MSK 12 ATUIMR 9 REPLAY_NUM Rollover Transmitter Send ERR_COR to Root Complex PE_DSTS 0 ERRCOR_STS 8 ATUISR 9 PE_DCTL 0 ERRC...

Page 278: ...upt Status Register Unit Interrupt Mask Bits Internal Bus Errors Master Abort on inbound requests Signal Completer Abort See Completer Abort above See Completer Abort above Completer Abort and ATUISR...

Page 279: ...tecture is designed to natively support both Hot Plug and hot remove of devices This section defines the usage model defined for all the ATU ATU supports the receipt and generation of Hot Plug message...

Page 280: ...ee distinct types of reset cold warm and hot The fundamental reset that occurs following initial power on is considered a hot reset The assertion of the PRST or WARM_RST pins are considered warm reset...

Page 281: ...xt Item Pointer Register MSI_Next_Ptr on page 430 the Section 4 7 23 Message Address Register Message_Address on page 432 the Section 4 7 24 Message Upper Address Register Message_Upper_Address on pag...

Page 282: ...ions of compliant VPD format 3 13 1 Configuring Vital Product Data Operation By default the 4138xx VPD functionality is not configured for operation Specifically the VPD Extended Capabilities List Ite...

Page 283: ...ess VPDAR 14 0 Four bytes are always transferred between this register and the VPD storage component 3 13 2 1 Reading Vital Product Data Using the fields defined in the VPD Capabilities List Item the...

Page 284: ...el XScale processor is triggered and bit 17 of the ATUISR is set Meanwhile the host processor polls the VPDAR register waiting for the Flag to be cleared Warning When any configuration writes to eithe...

Page 285: ...re Register Each Function can independently control this register PCI Express Device Control Register PE_DCTL Bit 14 12 Max_Read_Request_Size Use smallest programmed value when functions have differen...

Page 286: ...gister Each function can independently control these bit PCI Express Correctable Error Mask ERRCOR_MSK Entire Register Each function can independently control these bit Advanced Error Control and Capa...

Page 287: ...letion is reported in the function involved Bit 12 Received Target Abort Received Completer Abort Completion is reported in the function involved Bit 11 Signaled Target Abort Transmitted Completer Abo...

Page 288: ...ress Intel 413808 and 413812 I O Controllers in TPER Mode Developer s Manual October 2007 288 Order Number 317805 001US 3 15 Root Complex Functionality The 4138xx does not support Root Complex 3 16 Em...

Page 289: ...Note that all configuration read and write transactions is accepted on the internal bus as 32 bit transactions Refer to Chapter 19 0 Peripheral Registers The ATU is programmed via a Type 0 configurat...

Page 290: ...Bus Power Management Interface Specification Revision 1 1 compliance support the Power State Transition interrupt mask in bit 8 of the ATUIMR needs to be cleared It is the configuration software s res...

Page 291: ...ext Item Pointer Register Section 3 17 56 which indicates the configuration offset of an additional Extended Capabilities Header when supported In the ATU the Next Item Pointer Register is set to 00H...

Page 292: ...o additional Extended Capabilities Headers supported in the ATUs configuration space The following sections describe the ATU and Expansion ROM configuration registers Configuration space consists of 8...

Page 293: ...TU Register can be derived by adding the 4 KB address aligned Internal Bus Memory Mapped Register Range Offset Table 140 ATU Internal Bus Memory Mapped Register Range Offsets on page 293 to the Regist...

Page 294: ..._Cap_Ptr on page 314 03CH Section 3 17 24 ATU Interrupt Line Register ATUILR on page 315 03DH Section 3 17 25 ATU Interrupt Pin Register ATUIPR on page 316 03EH Section 3 17 26 ATU Minimum Grant Regis...

Page 295: ...bilities Register PCIE_DCAP on page 343 0D8H Section 3 17 59 PCI Express Device Control Register PE_DCTL on page 344 0DAH Section 3 17 60 PCI Express Device Status Register PE_DSTS on page 346 0DCH Se...

Page 296: ...it Memory Window Translate Value Register 3 OUMWTVR3 on page 380 328H Reserved 32CH Section 3 17 102 Outbound Configuration Cycle Address Register OCCAR on page 381 330H Section 3 17 103 Outbound Conf...

Page 297: ...imulate the interface of a standard mechanism currently used by existing application software PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw r...

Page 298: ...onse to a poisoned TLP received from PCI Express When cleared parity checking is disabled Note When the bit is cleared but the Poisoned TLP Mask is cleared in the PCI Express Uncorrectable Error Mask...

Page 299: ...Status 10 09 002 DEVSEL Timing Does not apply to PCI Express Hard wired to 0 08 02 Master Data Parity Error This bit is set by the ATU when its Parity Error Enable bit is set and either of the follow...

Page 300: ...fication Update ATU Revision identifies the 4138xx revision number PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro Attribute Legend RV Reserved PR Preserved RS Read...

Page 301: ...ault Description 07 00 00H ATU Cacheline Size specifies the system cacheline size in DWORDs Note This field is read write for legacy compatibility purposes but has no impact on any PCI Express device...

Page 302: ...Function Multi Function Device Identifies the 4138xx as a single function or multi function PCI device depending on the setting of the DF_SEL 2 0 strap during P_RST assertion Note The 4138xx can be co...

Page 303: ...it is set Setting this bit generates an interrupt to the Intel XScale processor to perform a software BIST function The Intel XScale processor clears this bit when the BIST software has completed with...

Page 304: ...ator and the Type Indicator Assuming IALR0 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prio...

Page 305: ...IABAR0 is set to indicate 32 bit addressability the IAUBAR0 register attributes are read only Prior to changing the Type Indicator in the IABAR0 to support 32 bit addressability the IAUBAR0 must be w...

Page 306: ...ts prefetching Scanning upwards starting at bit four bit twenty is the first one bit found The binary weighted value of this bit is 1 048 576 indicated that the device requires 1 Mbyte of memory space...

Page 307: ...m the PCI Express Link Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines the inbound translation window 1 from the PCI Express Link Inbound ATU Upper Base Address Register 1 N A...

Page 308: ...IALR1 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the user sho...

Page 309: ...s set to indicate 32 bit addressability the IAUBAR1 register attributes are read only By default the IAUBAR1 register has read only attributes Prior to changing the Type Indicator in the IABAR1 to sup...

Page 310: ...e Type Indicator Assuming IALR2 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host c...

Page 311: ...ressability or the Memory Space indicator of IABAR2 is set indicating I O space the IAUBAR2 register attributes are read only By default the IAUBAR2 register has read only attributes Prior to changing...

Page 312: ...ster uniquely identifies the add in board or subsystem vendor PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro...

Page 313: ...R to be programmed per PCI Local Bus Specification Revision 2 3 The Expansion ROM Base Address Register s programmed value must comply with the PCI programming requirements for address alignment Refer...

Page 314: ...Capability list In the case of the 4138xx this is the PCI Express Link Power Management extended capability as defined by the PCI Bus Power Management Interface Specification Revision 1 1 Table 163 AT...

Page 315: ...16 10H through 254 FEH are reserved 255 FFH indicates unknown or no connection Operating system or device driver can examine each device interrupt pin and interrupt line register to determine which sy...

Page 316: ...fault Description 07 00 01H Interrupt Used A value of 01H signifies that the ATU interface unit uses the INTA legacy interrupt message PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro...

Page 317: ...AT This register does not apply to PCI Express Table 167 ATU Maximum Latency Register ATUMLAT Bit Default Description 07 00 00H This register does not apply to PCI Express Hard wired to 0 PCI IOP Attr...

Page 318: ...he IALR0 makes the corresponding bit within the IABAR0 a read only bit which always returns 0 A value of 1 in a bit within the IALR0 makes the corresponding bit within the IABAR0 read write from PCI N...

Page 319: ...es for Base Address Registers on page 306 The default address allows the ATU to access the internal 4138xx memory mapped registers 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU...

Page 320: ...pondence A value of 0 in a bit within the IALR1 makes the corresponding bit within the IABAR1 a read only bit which always returns 0 A value of 1 in a bit within the IALR1 makes the corresponding bit...

Page 321: ...IABAR1 register s programmed value see Section 3 17 15 Determining Block Sizes for Base Address Registers on page 306 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a b...

Page 322: ...ne correspondence A value of 0 in a bit within the IALR2 makes the corresponding bit within the IABAR2 a read only bit which always returns 0 A value of 1 in a bit within the IALR2 makes the correspon...

Page 323: ...defined to be less than 1 Kbyte Hardware uses the PCI Address bits 09 08 as captured on the PCI address bus to drive the internal bus address 09 08 Table 175 Inbound ATU Translate Value Register 2 IAT...

Page 324: ...U Upper Translate Value Register 2 IAUTVR2 Bit Default Description 31 04 000 0000H Reserved 3 0 0H Inbound Upper ATU Translation Value 2 This value represents bits 35 to 32 of the internal bus address...

Page 325: ...ligned with the ERBAR register s programmed value see Section 3 17 15 Determining Block Sizes for Base Address Registers on page 306 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the A...

Page 326: ...his bit controls how completions are returned on the PCI Express interface 0 Max Payload Size setting is used to format completions Once enough data has accumulated to reach a Max Payload address boun...

Page 327: ...Number 15 02 Outbound Transaction Queue Busy 0 Outbound Transaction Queue Empty 1 Outbound Transaction Queue Busy Note This tracks outbound transactions and includes the Outbound Non Posted Outbound...

Page 328: ...etry When this bit is set the PCI Express interface of the 4138xx responds to all configuration cycles with a Completion Retry Status CRS condition When clear the 4138xx responds to the appropriate co...

Page 329: ...E_RCR on page 353 Generates the ATU Inbound Message Interrupt 26 0 Hot Plug Message Received This bit set when a Hot Plug message is received that changes the value of the Attention Indicator Status o...

Page 330: ...us PIE_STS register Note This read only bit is an OR of the unmasked PIE_STS bits Generates the ATU Error Interrupt 09 0 Correctable Error Message Transmitted Indicates a ERR_COR message was sent to t...

Page 331: ...ompletion Status is received by any function Generates the ATU Error Interrupt 00 0 Master Data Parity Error Interrupt Set when the Parity Error Response is enabled and any function transmits a Poison...

Page 332: ...en 1 the interrupt is masked 12 0 Root System Error Interrupt Mask When 1 the interrupt is masked 11 0 Reserved 10 0 Reserved Note ATUISR 10 is controlled by the PCI Interface Error Mask PIE_MSK regis...

Page 333: ...0 Reserved 01 On 10 Blink 11 Off Note These bits are updated regardless of the state of the Hot Plug Interrupt Mask in the ATUIMR 27 16 000H Reserved 15 02 Attention Button Pressed Control When this b...

Page 334: ...ed 5 Scrambling Disabled Status 0 Scrambling Active 1 Scrambling Disabled 4 Loopback Status 0 Loopback Disabled 1 Loopback Enabled 3 0 Disable Scrambling This controls the disable scrambling bit in th...

Page 335: ...and hence this register is set to 00H Table 186 VPD Capability Identifier Register VPD_Cap_ID Bit Default Description 07 00 03H Cap_Id This field with its 03H value identifies this item in the linked...

Page 336: ...mpleted Please see Section 3 13 Vital Product Data on page 282 for more details on how the 4138xx handles the data transfer 14 0 0000H VPD Address This register is written to set the DWORD aligned byt...

Page 337: ...he next capability MSI X capability list is located at off set B0H Note that the PM_Next_Item_Ptr can be written by the processor Table 190 PM_Capability Identifier Register PM_Cap_ID Bit Default Desc...

Page 338: ...wer Management State 9 12 D1_Support Set to 12 indicating that the 4138xx supports the D1 Power Management State 8 6 0002 Aux_Current This field is set to 0002 indicating that the 4138xx has no curren...

Page 339: ...the 4138xx Hard wired 0 14 9 00H Reserved 8 02 PME_En This bit is hard wired to read only 02 since this function does not support PME generation from any power state 7 2 0000002 Reserved 1 0 002 Powe...

Page 340: ...register is available for application specific purposes PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 341: ...t be initialized at P_RST assertion to Retry Type 0 configuration cycles bit 2 of PCSR Typically the Intel XScale processor would be enabled to boot immediately following P_RST assertion in this case...

Page 342: ...Link associated with this port is connected to a slot Only valid for root complex and switch downstream ports Hard wired to 0 Set to 1 for root complex this bit is initialized via strapping options 7...

Page 343: ...t a Power Indicator is implemented on the card or module 13 0 Attention Indicator Preset on Device When set indicates that an Attention Indicator is implemented on the card or module 12 0 Attention Bu...

Page 344: ...se phantom functions Hard wired to 0 8 0 Extended Tag Field Enable 4138xx does not generate 8 bit tags Hard wired to 0 7 5 000 Max_Payload_Size This field sets maximum TLP payload size for the device...

Page 345: ...eporting from the point of view of the respective function For a Root Port the reporting of non fatal errors is internal to the root No external ERR_NONFATAL message is generated 0 0 Correctable Error...

Page 346: ...evice Control register For devices supporting Advanced Error Handling errors are logged in this register regardless of the settings of the correctable error mask register For a multi function device e...

Page 347: ...8 00H Preserved 17 15 111b L1 Exit Latency Active State L1 Transition not supported 14 12 001b L0s Exit Latency 64ns 128ns 11 10 01b Active State Link PM Support 9 4 08H Maximum Link Width This device...

Page 348: ...this Link are operating with a distributed common reference clock This bit used to report the correct L0s and L1 Exit Latencies in the PCIE_LCAP register 5 0 Retrain Link As an end point this bit is...

Page 349: ...lex this read only bit indicates that Link training is in progress Hardware clears this bit once Link training is complete 10 0 Link Training Error As an endpoint this bit is hard wired to 0 For root...

Page 350: ...sis These registers should be initialized to 0 for ports connected to devices that are integrated on the system board 18 17 00b Reserved 16 15 00b Slot Power Limit Scale 14 7 00H Slot Power Limit Valu...

Page 351: ...pins Table 205 PCI Express Slot Control Register PE_SCR Bit Default Description 15 11 0H Reserved 10 0 Power Controller Control 9 8 00 Power Indicator Control 7 6 00 Attention Indicator Control 5 0 H...

Page 352: ...IOP in case a software solution can be implemented using the GPIO pins Table 206 PCI Express Slot Status Register PE_SSTS Bit Default Description 15 7 0H Reserved Zero 6 0 Presence Detect State 5 0 M...

Page 353: ...nterrupt when a fatal error ERR_FATAL message is received or a fatal error is detected by ATU This is only valid when operating as the root complex 1 0 System Error on Non Fatal Error Enable When set...

Page 354: ...e first PME requestor PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz rz ro ro rc rc ro ro ro ro ro ro ro ro ro r...

Page 355: ...w 16 0 Unexpected Completion As a receiver set whenever a completion is received that does not match the 4138xx s requestor ID or outstanding Tag The Header is logged 15 0 Completer Abort As a complet...

Page 356: ...eporting is masked 18 0 Malformed TLP Error Mask When 1 error reporting is masked 17 0 Receiver Overflow Error Mask When 1 error reporting is masked 16 0 Unexpected Completion Error Mask When 1 error...

Page 357: ...t Description 31 21 0 Preserved 20 0 Unsupported Request Error Status Severity 19 0 ECRC Check Severity 18 1 Malformed TLP Severity 17 1 Receiver Overflow Severity 16 0 Unexpected Completion Severity...

Page 358: ...Non Fatal Error Status 12 0 Replay Timer Timeout Status Set whenever a replay timer timeout occurs 11 9 0 Reserved Software must write 0 to these bits 8 0 REPLAY_NUM Rollover Status Set whenever the...

Page 359: ...ss Correctable Error Mask ERRCOR_MSK Bit Default Description 31 14 0 Preserved 13 1 Advisory Non Fatal Error Mask this bit is set by default to enable compatibility with software that does not compreh...

Page 360: ...ate until all bits in the ERRUNC_STS register are cleared PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr p...

Page 361: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Attribute Legend RV Reserved PR Preserved RS Read Set R...

Page 362: ...o ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro S S S S S S S S S S S S S S S S S S S S S S S S S S S S S...

Page 363: ...tal Uncorrectable error messages have been received 5 0 Non Fatal Error Messages Received This bit set when one or more Non Fatal Uncorrectable error messages have been received 4 0 First Uncorrectabl...

Page 364: ...rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro S S S S S S S...

Page 365: ...scription 31 0 0H PCI Express Device Serial Number Lower DW This register represents bits 31 to 0 of the EUI 64 identifier PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw ro rw ro rw ro rw ro...

Page 366: ...t determines the behavior when receiving a posted transaction that has poisoned data 0 Do not treat as an Advisory Error Send ERR_NONFATAL to root complex when error is detected 1 Treat as Advisory Er...

Page 367: ...PR Preserved RS Read Set RW Read Write RC Read Clear RO Read Only NA Not Accessible Internal Bus Address Offset 1F0H Table 228 Power Budgeting Data Select Register PWRBGT_DSEL Bit Default Description...

Page 368: ...cifies the power management state of the operating condition being described 00 D0 01 D1 10 D2 11 D3 A device returns 11b in this field and Aux or PME Aux in the Type register to specify the D3 Cold P...

Page 369: ...power budget for the device is included within the system power budget Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions when this bit is set PC...

Page 370: ...wer thermal numbers for 4138xx Data Select PWRBGT_INFOx Register Offset Data Select PWRBGT_INFOx Register Offset 00h 0 200H 0Ch 12 230H 01h 1 204H 0Dh 13 234H 02h 2 208H 0Eh 14 238H 03h 3 20CH 0Fh 15...

Page 371: ...s 31 16 from the Outbound I O Window Translate Value Register OIOWTVR Table 232 Outbound I O Base Address Register OIOBAR Bit Default Description 31 12 0 FFFDH Outbound I O Base Address This value rep...

Page 372: ...ress Register OIOBAR with the a fixed length of 64 Kbytes Table 233 Outbound I O Window Translate Value Register OIOWTVR Bit Default Description 31 16 0000H Outbound I O Window Translate Value Used to...

Page 373: ...when A 35 32 matches OUMBAR0 3 0 30 28 0002 Outbound Window 0 Function Number Mapping Errors with Outbound Memory Window 0 transactions PCI or Internal Bus is associated with the function number conta...

Page 374: ...pace When this register is all zero then a 3DW header is generated on the PCI Express Link Table 235 Outbound Upper 32 bit Memory Window Translate Value Register 0 OUMWTVR0 Bit Default Description 31...

Page 375: ...32 matches OUMBAR1 3 0 30 28 0002 Outbound Window 1 Function Number Mapping Errors with Outbound Memory Window 1 transactions PCI or Internal Bus is associated with the function number contained in t...

Page 376: ...pace When this register is all zero then a 3DW header is generated on the PCI Express Link Table 237 Outbound Upper 32 bit Memory Window Translate Value Register 1 OUMWTVR1 Bit Default Description 31...

Page 377: ...5 32 matches OUMBAR2 3 0 30 28 0002 Outbound Window 2 Function Number Mapping Errors with Outbound Memory Window 2 transactions PCI or Internal Bus are associated with the function number contained in...

Page 378: ...the 64 bit host address space When this register is all zero then a 3DW header is generated on the PCI bus Table 239 Outbound Upper 32 bit Memory Window Translate Value Register 2 OUMWTVR2 Bit Default...

Page 379: ...5 32 matches OUMBAR3 3 0 30 28 0002 Outbound Window 3 Function Number Mapping Errors with Outbound Memory Window 3 transactions PCI or Internal Bus are associated with the function number contained in...

Page 380: ...the 64 bit host address space When this register is all zero then a 3DW header is generated on the PCI bus Table 241 Outbound Upper 32 bit Memory Window Translate Value Register 3 OUMWTVR3 Bit Default...

Page 381: ...to initiate the configuration transaction on the PCI Express Link Table 242 Outbound Configuration Cycle Address Register OCCAR Bit Default Description 31 24 00H Bus Number 23 19 00H Device Number 18...

Page 382: ...turned directly from the ICPLDQ to the Intel XScale processor and is never actually entered into the data register which does not physically exist The OCCDR is only visible from 4138xx internal bus ad...

Page 383: ...endpoint usage and 5 for Root Complex modes Table 244 Outbound Configuration Cycle Function Number OCCFN Bit Default Description 31 03 0000 0000H Reserved 02 00 000 Configuration Cycle Function Number...

Page 384: ...Type 1 messages are silently discarded Vendor_Defined message format is shown below in Figure 38 Table 245 Inbound Vendor Defined Message Header Register0 IVMHR0 Bit Default Description 31 24 00H Hea...

Page 385: ...red or the mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set then Vendor_Defined Type 0 messages are treated as unsupported requests and Vendor_Defined Type 1 messages...

Page 386: ...ed or the mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set then Vendor_Defined Type 0 messages are treated as unsupported requests and Vendor_Defined Type 1 messages...

Page 387: ...nbound posted queues until the status bit is cleared or mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set Vendor_Defined Type 0 messages are treated as unsupported req...

Page 388: ...header no data 1 11 4DW header with data 28 27 10 Type 4 3 10 indicates this is a vendor_defined message Hard wired to 10 26 24 000 Type 2 0 Message Routing The valid encodings are specified below 00...

Page 389: ...1 OVMHR1 Bit Default Description 31 24 00H Requester ID Bus number This value is copied from the Bus number field in the PCISR 23 19 0_0000 Requester ID Device Number This value is copied from the De...

Page 390: ...th is 0 a write to the OVMPR is still required to initiate the TLP but the data written is ignored Vendor_Defined message format is shown in Figure 38 Table 252 Outbound Vendor Defined Message Header...

Page 391: ...r_Defined message format is shown in Figure 38 Note This register does not physically exist It is simply a write port A read to this register is not claimed by the ATU and causes a data abort This add...

Page 392: ...chapter for remaining details of Initiator ID 27 0 General Device Error GDE This bit is set when an error can not be isolated to a single function and is being logged against all function 26 24 0002 P...

Page 393: ...detected The Header is logged 17 0 Receiver Overflow Set when PCI Express receive buffers overflow 16 0 Unexpected Completion As a receiver set whenever a completion is received that does not match th...

Page 394: ...reporting is masked 19 0 ECRC Check Error Mask When 1 error reporting is masked 18 0 Malformed TLP Error Mask When 1 error reporting is masked 17 0 Receiver Overflow Error Mask When 1 error reporting...

Page 395: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Read...

Page 396: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Re...

Page 397: ...Attributes Attributes 28 24 20 16 12 8 4 0 31 rv rv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro...

Page 398: ...transactions on the internal bus to the MU on behalf of the external PCI agents The MU has two distinct messaging mechanisms Each allows a host processor or external PCI agent and the 4138xx to commu...

Page 399: ...f the 4138xx Multi word transactions made by an external PCI agent results in an error being sent to the external PCI agent Refer to the ATU chapters for more details on how the ATUs respond to an int...

Page 400: ...24H 0028H 002CH Outbound Interrupt Status Register Outbound Interrupt Mask Register Reserved 2 Doorbell Registers and 0034H 0038H 003CH 0040H Reserved Reserved Reserved 2 Queue Ports 0044H 0048H 004CH...

Page 401: ...d MU Configuration Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved MSI Inbound Message Register 4000H 4010H 401CH 4018H 4014H 4020H 4024H 4028H 402CH 4034H 4038H 403CH 4040H 40...

Page 402: ...2 1 Transaction Ordering From a PCI standpoint the Messaging Unit is a piece of the ATU and therefore must maintain ordering requirements against ATU transactions Transaction ordering is achieved for...

Page 403: ...terrupt is recorded in the Outbound Interrupt Status Register The interrupt causes the Outbound Message Interrupt bit to be set in the Outbound Interrupt Status Register This is a Read Clear bit that...

Page 404: ...written to the Outbound Doorbell Register The interrupt is cleared when an external PCI agent writes a value of 1 to the bits in the Outbound Doorbell Register that are set Writing a value of 0 to any...

Page 405: ...saging Unit like the ATU encounters error conditions on the host I O interface as well as the internal bus interface As a host I O interface target all host I O interface errors are captured and recor...

Page 406: ...s each MSI capable device is allowed Then software writes the Message Address Registers and the Message Upper Address Registers when Message Address is above the 4G address boundary12 and the Message...

Page 407: ...fset Register and MSI X Pending Bits Array Register to determine the locations these structures After gathering this data from all of the MSI X capable devices in the system the configuration software...

Page 408: ...ult in the assertion of the P_INTx output pin However all the P_INT A D pins are functional for steering of interrupts from other PCI devices that may not be MSI capable MSI X Table and Pending Bits A...

Page 409: ...rrupt is level triggered the interrupt service routine does not drop out of the service routine until the interrupt signal is deasserted This insures that an interrupt is not missed MSI interrupts are...

Page 410: ...ound address window of the ATU Inbound Message 0 Register Inbound Message 1 Register Outbound Message 0 Register Outbound Message 1 Register Inbound Doorbell Register Inbound Interrupt Status Register...

Page 411: ...38H Section 4 7 9 Inbound Reset Control and Status Register IRCSR on page 419 403CH Section 4 7 10 Outbound Reset Control and Status Register ORCSR on page 420 4048H Section 4 7 11 MSI Inbound Message...

Page 412: ...pt to the Intel XScale processor may be generated PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 413: ...the IDR register can only be set by an external Host I O Interface agent and can only be cleared by the Intel XScale processor Table 268 Inbound Doorbell Register IDR Bit Default Description 31 02 Err...

Page 414: ...on 05 02 Outbound Free Queue Full Interrupt This bit is set when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full An Error interrupt is generated for this conditi...

Page 415: ...en set this bit masks the interrupt generated by the MU hardware when an Index Register has been written after a Host I O Interface transaction 05 02 Outbound Free Queue Full Interrupt Mask When set t...

Page 416: ...nterrupt C When set this bit causes the P_INTC signal to be asserted or a Message signaled Interrupt is generated when enabled When this bit is cleared the P_INTC signal is deasserted 29 02 PCI Interr...

Page 417: ...bit and the interrupt the PCI Interrupt C bit must be cleared 05 02 PCI Interrupt B This bit is set when the PCI Interrupt B bit is set in the Outbound Doorbell Register To clear this bit and the int...

Page 418: ...asks the PCI Interrupt C signal when the PCI Interrupt C bit in the in the Outbound Doorbell Register is set 05 02 PCI Interrupt B Mask When set this bit masks the PCI Interrupt B signal when the PCI...

Page 419: ...ailed descriptions of the RCSR register Table 274 Inbound Reset Control and Status Register IRCSR Bit Default Description 31 02 00000000H Reserved 01 02 Coordinated Reset CR This bit is valid when the...

Page 420: ...rotocol is not implemented this bit is always zero Note The state of this bit is saved in the Reset Cause Status Register RCSR when an internal bus reset occurs Refer to the Exception Initiator and Bo...

Page 421: ...0 3 Table 276 MSI Inbound Message Register MIMR Bit Default Description 31 16 0000H Reserved 15 02 Core Select Bit This bit is used to select the Intel XScale processor which is the target of the MSI...

Page 422: ...K entries 16 Kbytes to 64 K entries 256 Kbytes and there are four Circular Queues This register also contains the upper four bits of the 36 bit QBR address Local memory is 36 bit addressable Table 27...

Page 423: ...nd MSI X Data Structures Note The default values of MUBAR MUBAR are programmed to match the default values programmed in the Inbound ATU Translate Value Register 0 IATVR0 Inbound ATU Upper Translate V...

Page 424: ...o match the default values programmed in the Inbound ATU Translate Value Register 0 IATVR0 Inbound ATU Upper Translate Value Register 0 IAUTVR0 This allows the MU registers to be mapped in the first 8...

Page 425: ...ddress This field contains the lower 30 bits of the MSI X Message Address 01 00 002 Reserved PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 426: ...000H Message Upper Address This field contains the upper 32 bits of the MSI X Message Address PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r...

Page 427: ...essage Data This field contains the message data for this Table entry PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r...

Page 428: ...ved 00 12 Message Vector Control This bit when set prohibits the sending an MSI X message using this entry PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv rv rv rv rv rv rv rv rv rv rv rv rv...

Page 429: ...ng Bits Array Register M_MPBAR Bit Default Description 31 08 0000 000H Reserved 07 00 000000002 Pending Bits Array Any bit that is set indicates that the associated MSI X message is scheduled to be se...

Page 430: ...r to the Peripheral Registers Chapter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 286 MSI N...

Page 431: ...field is set to 12 indicating that the 4138xx is capable of generating a 64 bit message address 6 4 0002 Multiple Message Enable System software writes to this field to indicate the number of message...

Page 432: ...ation space of the Address Translation Unit that is setup as an endpoint Table 288 Message Address Register Message_Address Bit Default Description 31 2 00000000H Message Address DWORD aligned Message...

Page 433: ...eral Registers Chapter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 289 Message Upper Addres...

Page 434: ...n endpoint Table 290 Message Data Register Message_Data Bit Default Description 15 00 0000H Message Data System software specifies a 16 bit value to be transferred during the data phase of an MSI writ...

Page 435: ...col Addendum to the PCI Local Bus Specification Revision 2 0 Note Refer to the Peripheral Registers Chapter for the default internal bus address This register is part of the configuration space of the...

Page 436: ...sters Chapter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 292 MSI X Next Item Pointer Regis...

Page 437: ...When set all the vectors in the MSI X Table are globally masked regardless of the per vector Mask Bit states in the Vector Control Register of the MSI X Table entries 13 11 0002 Reserved 10 00 0000000...

Page 438: ...ccupies 8 KByte of address space and must overlap the address space defined by the ATU Value and the ATU Limit registers Equation MSI X Table Offset 31 13 ATU Limit_Register 31 0 MU_Bar 31 0 13 Note T...

Page 439: ...ng Unit occupies 8 KByte of address space and must overlap the address space defined by the ATU Value and the ATU Limit registers Equation MSI X Table Offset 31 13 ATU Limit_Register 31 0 MU_Bar 31 0...

Page 440: ...to be generated Table 296 MU MSI X Control Register X MMCRx Bit Default Description 31 01 0000 0000H Reserved 00 02 MU MSI X Single Message Vector This bit when set causes only a single MSI X Message...

Page 441: ...ointer registers before setting the Circular Queue Enable bit Table 297 Inbound MSI Interrupt Pending Registers IMIPR 0 3 Bit Default Description 31 00 0000 0000H Inbound MSI Pending Interrupts Each b...

Page 442: ...he SRAM DMA SDMA Unit 5 2 Overview The SRAM DMA SDMA unit provides a means for memory to be transferred between local memory SRAM and host memory through the PCIe bus The SDMA provides two separate ch...

Page 443: ...ast DMA operation requested Firmware then writes the Host Addresses Local Addresses and the Byte Count The firmware then sets the CHGO bit to start the DMA Upon completion of the DMA operation the fir...

Page 444: ...r and assuring the upper and lower counts are equal x b 0xFFD98238 l 0x4 4 2 Set bit 30 in the byte swap register to disable byte swapping mfill b 0xFFD98200 l 0x4 p 0x40000000 3 Set the host destinat...

Page 445: ...Interrupt Directed to internal FIQ INTSRC2 bit 13 SDMA Error Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL2 1 Interrupting and steered to internal IRQ exce...

Page 446: ...ation Upper Address Register L2H_DUAR on page 447 Section 5 4 3 LocalToHost Source Lower Address Register L2H_SLAR on page 448 Section 5 4 4 LocalToHost Byte Count Register L2H_BCR on page 449 Section...

Page 447: ...a rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na Intel XScale Micro...

Page 448: ...e written as zero 19 00 00000H Source Lower Address Register SLAR Read Write Specifies first source local memory starting byte address that SDMA Processor uses to read data The field decodes a 1MB loc...

Page 449: ...rved Must be written as zero 12 00 000H Byte Count Register BCR This field specifies the length in bytes that is for the data to be transferred The maximum transfer count value is 4096 bytes 1000H Thi...

Page 450: ...is channel the Interrupt Counter is incremented and an interrupt is asserted Firmware reads the Interrupt Counter of each channel to determine which one raised the interrupt Firmware then writes back...

Page 451: ...this bit to begin the DMA operation This bit must be cleared while the DMA registers are being set up The CHGO bit is set by firmware to begin the DMA operation When the DMA operation begins the hardw...

Page 452: ...v na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write RC Read Clear RO Read Only NA N...

Page 453: ...rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na Intel XScale Microarchitecture...

Page 454: ...tware reset 15 13 0002 Reserved Must be written as zero 12 00 000H Byte Count Register BCR This field specifies the length in bytes that is for the data to be transferred The maximum transfer count va...

Page 455: ...channel the Interrupt Counter is incremented and an interrupt is asserted Firmware reads the Interrupt Counter of each channel to determine which one raised the interrupt Firmware then writes back the...

Page 456: ...this bit to begin the DMA operation This bit must be cleared while the DMA registers are being set up The CHGO bit is set by firmware to begin the DMA operation When the DMA operation begins the hardw...

Page 457: ...p Control Register H2L_BSCR Bit Default Description 31 00 Reserved 30 00 Byte Swap Disable Read Write This bit must be set to prevent SDMA transfers from byte swapping 29 0 00 Reserved Coprocessor IOP...

Page 458: ...GPIO defines communication between an initiator and a target The target typically converts output signals into multiple parallel LED signals and provides inputs frsom general purpose inputs Figure 43...

Page 459: ...I O Controllers in TPER Mode October 2007 Developer s Manual Order Number 317805 001US 459 SGPIO Unit Intel 413808 and 413812 Figure 43 SGPIO Bus Overview Initiator SClock SLoad SDataOut SDataIn Targe...

Page 460: ...xample in Figure 44 shows four drives and five drives The bit stream need not be the same length every time 6 2 1 SGPIO SClock Output Signal SClock is a free running clock running at a fixed frequency...

Page 461: ...SDataIn signal carries input bits associated with devices on the target For example on 4138xx the SGPIO can receive up to three bits per device and up to eight devices on the target thus is able to re...

Page 462: ...GPIO units SClock is the output clock of the SGPIO interface and runs at a fixed 99 8 KHz Load Clock this clock is used internally to load the internal latches This clock runs at 1 24 the SClock rate...

Page 463: ...e outputs can be optionally inverted Each output bit can be independently selected using the Table 328 SGPIO Output Data Select Register 0 7 x SGODSR 0 7 x on page 484 The selected output can in turn...

Page 464: ...ENG Status Programmable Pattern A Programmable Pattern B Inverting Logic XOR Control bit6 in SGODSR 0 7 x Control bits 5 4 in SGODSR 0 7 x JOG Logic Control bit7 in SGODSR 0 7 x Pre Conditioning Logic...

Page 465: ...rive4 OD0 Activity 5 Protocol Engine Activity 0 Programmable Pattern A Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Drive0 OD1 Fixed High Drive4 OD1 Protocol Engine...

Page 466: ...ttern B Programmable Pattern B Fixed High Drive3 OD0 Fixed High Drive7 OD0 Protocol Engine Activity 3 Protocol Engine Activity 6 Programmable Pattern A Programmable Pattern A Programmable Pattern B Pr...

Page 467: ...age 484 When enabled this feature monitors the input signal and if the input signal is detected low for about four seconds it will be forced high for a 250 ms duration 6 4 1 2 Protocol Engine Pre Cond...

Page 468: ...tput Data Select Register 0 7 x SGODSR 0 7 x on page 484 The blink rate generator is clocked using an 8 Hz clock and allows the user to program a low and a high duration time using two 4 bit fields lo...

Page 469: ...neously In direct LED mode programming the multiplexer allows any four drive output signals to be selected and driven on direct LED pins The programmable feature of SGPIO allows for either SGPIO unit...

Page 470: ...e simply programmed in that order in Table 324 SGPIO Start Drive Upper Register x SGSDURx on page 480 Table 315 shows the outputs 7 0 of the multiplexer block for SGPIO unit 1 Table 314 Example 1 Mult...

Page 471: ...on page 480 Table 317 shows the outputs 7 0 of the multiplexer block for SGPIO unit 1 Table 316 SGPIO Unit 0 Multiplexer Block Outputs for Example 2 Multiplexe r Block Output Output 7 Output 6 Output...

Page 472: ...lid signals only for product types that support fibre channel ports Multiplexers are controlled per product type For example a 4138xx that Table 318 SGPIO Unit 0 Pin Multiplexing Activity Pin Shared P...

Page 473: ...ping S_ACT 6 SDATAIN 1 S_STAT 6 SDATAOUT 1 S_ACT 7 TXRATE6 0 S_STAT 7 TXRATE6 1 S_ACT 4 SCLOCK 1 S_STAT 4 SLOAD 1 S_ACT 5 TXRATE4 0 S_STAT 5 TXRATE4 1 TXRATE6 0 TXRATE6 1 TXRATE4 0 TXRATE4 1 SDATAOUT...

Page 474: ...aligned global PMMR Block Default for the 512 KB aligned PMMR Block is 0 FFD8 0000H defined by the PMMRBAR register See also Chapter 19 0 Peripheral Registers Table 320 SGPIO Memory Mapped Rejecters S...

Page 475: ...y Enable For SGPIO unit 0 When this bit is set the SGPIO bus pins S_ACT 0 S_STAT 0 S_ACT 2 and S_STAT 2 are used for SGPIO signaling When cleared the SGPIO pins are used for direct LED controls For SG...

Page 476: ...to program the high duration time in millisecond for pattern B Bits Duration millisecond 00002 125 00012 250 00102 375 00112 500 01002 625 01012 750 01102 875 01112 1000 10002 1125 10012 1250 10102 13...

Page 477: ...w duration time in millisecond for pattern A Bits Duration millisecond 00002 125 00012 250 00102 375 00112 500 01002 625 01012 750 01102 875 01112 1000 10002 1125 100012 1250 10102 1375 10112 1500 110...

Page 478: ...e 469 Bits Output Number 0002 0 0012 1 0102 2 0112 3 1002 4 1012 5 1102 6 1112 7 11 02 Reserved 10 08 0102 Output 2 Select Bits This bit field selects which Input 0 7 of the Multiplexer Block is selec...

Page 479: ...2 0112 3 1002 4 1012 5 1102 6 1112 7 Table 323 SGPIO Start Drive Lower Register x SGSDLRx Sheet 2 of 2 Bit Default Description Coprocessor IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv na rv na...

Page 480: ...469 Bits Output Number 0002 0 0012 1 0102 2 0112 3 1002 4 1012 5 1102 6 1112 7 11 02 Reserved 10 08 1102 Output 6 Select Bits This bit field selects which Input 0 7 of the Multiplexer Block is select...

Page 481: ...02 2 0112 3 1002 4 1012 5 1102 6 1112 7 Table 324 SGPIO Start Drive Upper Register x SGSDURx Sheet 2 of 2 Bit Default Description Coprocessor IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv na rv...

Page 482: ...ult Description 31 16 0000H Reserved 15 02 Reserved 14 12 0002 Drive 3 input data 11 02 Reserved 10 08 0002 Drive 2 input data 07 02 Reserved 06 04 0002 Drive 1 input data 03 02 Reserved 02 00 0002 Dr...

Page 483: ...ut data 03 02 Reserved 02 00 0002 Drive 4 input data Coprocessor IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na r...

Page 484: ...05 04 to be inverted When cleared the selected input is not altered 05 04 002 OD1 Input Select This field selects the input that drives output OD1 of Drive N where N 0 7 Bits Selection 002 Fixed High...

Page 485: ...nal busses on 4138xx and therefore there are two system controllers implemented one for the North Internal Bus and one for the South Internal Bus The north internal bus SC controls the two Intel XScal...

Page 486: ...gent The SC actually frames the address transactions and therefore drives the address strobe along with the address bus grant The assertion of address strobe indicates that a valid XSI bus command is...

Page 487: ...d for the purpose of logging transaction errors Table 329 lists the encoded initiator IDs Table 329 Intel 413808 and 413812 I O Controllers in TPER Mode Initiator IDs Internal Bus Initiator Initiator...

Page 488: ...provides an enable bit which must be set by software and is reset by hardware This provides a way of injecting an error only once a one shot process For example error is injected only during the addr...

Page 489: ...initiators are making address requests In addition these same Initiator IDs can be used when injecting data parity error when these initiators are pushing data during writes Table 331 Data Parity Tes...

Page 490: ...e also claims transactions that target the Bridge memory mapped registers Intel XScale processor transactions that target the Bridge memory mapped registers are also propagated to the south internal b...

Page 491: ...ly when the address is aligned on a 32 byte boundary In other words for a non 32 byte aligned address the sum of the non aligned address and byte count has to be less than the next 32 byte aligned add...

Page 492: ...he Bridge Limit Register BWLR Transactions on the south internal bus that target this memory window are claimed and forwarded to the north internal bus The South Bridge Interface also claims transacti...

Page 493: ...rite Requests targeting only the north interface of the Bridge For example outbound write requests from the north internal bus to the south internal bus Although the bridge must allow write requests t...

Page 494: ...nternal bus to the south internal bus as either a read completion or write request the bridge generates data parity as the data enters the north bridge interface The data and its parity are stored in...

Page 495: ...ered an error by performing a target abort during the read completion Address Request Error on the north internal bus interface This condition may happen when a target on the north internal bus detect...

Page 496: ...uring the address request For example the target may indicate that the byte count is out of range or the target detected an address parity error For a write request the bridge logs the address request...

Page 497: ...Internal Bus Arbitration Control Register provides controls for both the North and South Internal address busses The south internal bus address and data test registers are used to force address or da...

Page 498: ...idge on the south interface The Bridge Error Status register indicates the type of error that was encountered by the bridge on either the north or south interfaces The Bridge Error Address and Error U...

Page 499: ...ts 15 0 control the address initiators on the north internal address bus and bits 31 16 control the address initiators on the south internal address bus Warning Since the internal address arbiter park...

Page 500: ...s are not granted the south internal address bus when this bit is set 0 Enabled 1 Disabled 15 03 000H Reserved 02 02 Reserved 01 02 XSC coreID1 control this bit controls coreID1 The Intel XScale proce...

Page 501: ...Default Description 31 21 000H Reserved 20 16 000002 Address Parity Mask bits Each bit of the generated address parity is XORed with the appropriate bits in this mask field before the parity bits are...

Page 502: ...fault Description 31 16 00002 Data Parity Mask bits Each bit of the generated data parity is XORed with the appropriate bits in this mask field before the parity bits are driven on the south internal...

Page 503: ...0 FFD8 0000H Table 337 Peripheral Memory Mapped Register Base Address Register PMMRBAR Bit Default Description 31 15 0000 1111 1111 1101 12 PMMR Base Address These bits define the starting address of...

Page 504: ...bit 20 through bit 31 of the base address from the Bridge Base Address Register BBAR are relevant to the Bridge when decoding Memory Window Warning Care must be exercised when modifying the Bridge Ba...

Page 505: ...e granularity of the memory block size For instance when a 64 Kbyte memory window size is selected the base address needs to be 64 Kbyte address aligned i e bits 15 12 of the base address are required...

Page 506: ...ble 340 Bridge Window Upper Base Address Register BWUBAR Bit Default Description 31 04 0000 000H Reserved 03 00 0H Bridge Upper Memory Window Base Address These bits are the upper 4 bits of the 36 bit...

Page 507: ...Table 341 Bridge Limit Register BWLR Bit Default Description 31 12 FFF0 0H Bridge Memory Window Limit This value determines the memory range required for the Bridge Memory Window Defaults to a 1MB Me...

Page 508: ...when a South Internal Bus Error is detected When cleared an interrupt to the Intel XScale processor is not signaled when a South Internal Bus Address Error is detected Note This enable applies to all...

Page 509: ...gs one of the errors as there is only one set of log registers 01 02 Error N Detected Indicates that the Bridge detected an error on either the north or south internal bus interface while BECSR 0 was...

Page 510: ...e 36 bit address of the request that resulted in an error PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro n...

Page 511: ...ory Interface 128 bit wide port with data parity protection ECC supported on 32 bit data width The SRAM interface provides a direct connection to a high bandwidth and reliable memory subsystem An 7 bi...

Page 512: ...cted within the memory array the SMCU must correct the error if possible while delivering the data to the initiator Correcting the memory location is referred to as scrubbing the array The SMCU relies...

Page 513: ...ce connects to the SMCU using a separate read port and write port Each port provides a 128 bit data path The ports are described in the next sub sections 8 3 1 1 North Internal Bus Ports The North Int...

Page 514: ...ction queue 8 3 1 3 Memory Transaction Queues There are one set of transaction queues for transactions which address the SRAM Memory Space from the north internal bus The transaction queues are locate...

Page 515: ...RAM reads and writes For reads this logic compares the ECC codes read with the locally generated ECC code If the codes mismatch then the Error Correction Logic determines the error type For a single b...

Page 516: ...ort Coherency With the queueing of SRAM transactions in multiple ports coherency of memory must be maintained The SMARB maintains memory coherency by ensuring that all writes to a given memory address...

Page 517: ...if required Refer to Section 357 SRAM Parity Control and Status Register SPARCSR on page 542 8 3 2 2 SRAM Read Sequence Read transactions require ECC codes to be calculated and compared with the ECC...

Page 518: ...mine if the transaction should be claimed If the address falls in the SRAM address range indicated by the SRAMBAR and SRAMUBAR the SMCU claims the transaction 2 Once the SMARB selects the highest prio...

Page 519: ...plements a 256 bit data path to the SRAM array but a 7 bit error correction code per every 32 bit datum For example SCB0 6 0 for DQ 31 0 SCB1 6 0 for DQ 63 32 SCB2 6 0 for DQ 95 64 and so on resulting...

Page 520: ...he new data and ECC else Partial Write Read entire 32 bit data word from memory Merge the new data portion with the data from memory Generate the new ECC with the G matrix Write new data and ECC Figur...

Page 521: ...is written back to the array If a multi bit error is detected the SMCU causes an interrupt to the core by writing to the MCISR The memory location is overwritten by the SMCU with the error data but v...

Page 522: ...orting is enabled Interrupt core for software scrubbing else uncorrectable if the read cycle is not part of a RMW cycle read Target Abort the Internal Bus read transaction else write requiring RMW Mer...

Page 523: ...ough the ECC hardware for a read transaction Figure 59 ECC Read Data Flow ECC 256 bit Data Path SMCU SRAM Memory Array ECC Memory D 31 0 H Matrix Look Up Table Caculate ECC G Matrix Caculate Syndrome...

Page 524: ...its E 6 0 Data Bit Syndrome ECC Check Bits E 6 0 E 6 E 5 E 4 E 3 E 2 E 1 E 0 E 6 E 5 E 4 E 3 E 2 E 1 E 0 E6 40H X D15 45H X X X E5 20H X D14 51H X X X E4 10H X D13 43H X X X E3 08H X D12 61H X X X E2...

Page 525: ...upt to the core Write cycles are posted to the memory transaction queues and already completed to the initiating master For write cycles with a multi bit error and ECC Error reporting is enabled the S...

Page 526: ...ng the G Matrix in Figure 58 the SRAM Control Block creates each check bit by XORing the appropriate bits in the row Using 9ABC DEF0H the ECC code generated is 11H This code is written with the data t...

Page 527: ...ge 526 explains how software is responsible for correcting an error in the memory array once it has been detected by the ECC logic The SMCU implements the SECTST register providing the programmer the...

Page 528: ...enters the port and before it is written to the data queue For read requests made to an SMCU port the direct memory port interface performs the following tasks before delivering data checks for ECC on...

Page 529: ...ated by bit XORing the data bits as shown in Table 347 As an example the parity calculation for the lowest order byte of the data bus D 7 0 is calculated as follows Note The direct memory port does no...

Page 530: ...Note The direct memory port does not support address parity Equation 16 DATA_PARITY_RESULT D_PARITY0 XOR D 0 XOR D 1 XOR D 2 XOR D 3 XOR D 4 XOR D 5 XOR D 6 XOR D 7 XOR BE 0 A non zero result from the...

Page 531: ...ulting in the error in SELOG 23 16 and interrupts the core If the SMCU detects an ECC error during a read or write cycle SMCISR 0 is set to 1 Whenever the SMCU toggles the SMCISR 0 bit from 0 to 1 an...

Page 532: ...bit error SMCU records requester of transaction that resulted in an error in SELOG 23 16 The SMCU loads SELOG 7 0 with the syndrome that indicated the error The SMCU loads SECAR 31 2 and SECUAR with...

Page 533: ...the internal bus initiator of a multi bit error by returning a target abort The SMCU records the error type in SELOG and the address in SECAR and SECUAR When SMCU detects a multi bit error during a wr...

Page 534: ...error is detected on any of the SMCU ports and parity is enabled the SMCU records the requesting port that detected the parity error in the SPCSR 19 16 and interrupts the core Refer to the Section 8 6...

Page 535: ...ontroller Register Section Register Name Acronym Page Section 8 6 1 SRAM Base Address Register SRAMBAR on page 536 Section 8 6 2 SRAM Upper Base Address Register SRAMUBAR on page 536 Section 8 6 3 SRA...

Page 536: ...SECR This register programs the SMCU error correction and detection capabilities The configuration depends on the application s needs but a typical configuration is ECC Mode Enabled Enable multi bit e...

Page 537: ...e bit error correction 01 02 Multi Bit Error Reporting Enable Enables or disables the reporting interrupt generation of a multi bit error condition 0 Disable multi bit error reporting 1 Enable multi b...

Page 538: ...eet 1 of 2 Bit Default Description 31 28 0H Upper ECC Address The upper 4 bits of the 36 bit ECC Address is stored in this 4 bit field when an ECC error is logged For example the lower 32 bits are log...

Page 539: ...red during a read or write transaction 0 Read error 1 Write Error 11 09 0002 Reserved 08 02 ECC Error Type Indicates the type of error that occurred at this address 0 Single Bit Error 1 Multi Bit Erro...

Page 540: ...Table 354 SRAM ECC Address Register SEAR Bit Default Description 31 02 0 Error Address Stores the lower 30 bits of the address that resulted in a single bit or multi bit error 01 00 002 Reserved PCI...

Page 541: ...e locations result in an ECC error Table 356 SRAM ECC Test Register SECTST Bit Default Description 31 07 00 0000H Reserved 06 00 00H ECC Mask 7 bit ECC mask Each bit of the generated ECC is XORed with...

Page 542: ...ATUE 01012 Application DMAs 01102 Reserved 01112 Messaging Unit 10002 Reserved 10012 SMBus All other IDs are reserved Note This field is only valid when the Port ID in this register bits 19 16 indica...

Page 543: ...ontents of associated log register For error details see Section 8 3 4 Byte Parity Checking and Generation on page 528 Table 358 SRAM Parity Address Registers SPAR Bit Default Description 31 02 0000 0...

Page 544: ...rrupt Status Register SMCISR Bit Default Description 31 05 0000 000H Reserved 09 02 Parity N Indicates that the SMCU detected a Parity error while SMCISR 8 was set 0 No error detected 1 Error detected...

Page 545: ...ins the following Peripheral Bus signals which consist of address data control status Peripheral Bus Read and write transactions Peripheral Bus configuration and Flash Memory Support Registers This ch...

Page 546: ...the PBI Write requests are limited to a maximum of 4 bytes only and must not span a DWORD boundary The PBI signals an address error when a write request has its byte count out of range The peripheral...

Page 547: ...evice enables and direction All output control status signals are three state A peripheral read may be either non burst or burst A non burst read ends after one data transfer to a single location When...

Page 548: ...memories in a manner consistent with the programmed bus width 8 bit region A 1 0 provide the demultiplexed byte address for a read burst 16 bit region A 2 1 provide the demultiplexed short word addre...

Page 549: ...ess in the bursted transaction Address bits A 24 3 provide the upper address of the current access and is a constant during the address Ta wait state Tw and data cycles Td cycles A 2 1 are used for an...

Page 550: ...by programmable wait state profiles to support Flash devices Any write transactions issued to a Flash address space window must always represent a single flash bus data cycle strb strh The peripheral...

Page 551: ...t Flash The definition of recovery wait states are the number of cycles between the data arrival on D 7 0 and the address for the next Peripheral transaction Address to data and recovery wait states a...

Page 552: ...respectively Refer to Table 362 for the programmable address to data data to data and recovery wait states These numbers are based on a 66 MHz internal clock for the PBI interface Figure 66 120 ns Fl...

Page 553: ...e read requests the PBI supports multi byte write requests by breaking the writes on the PBI bus into multiple single data write transactions The number of single data write transactions initiated on...

Page 554: ...tion Register Name Acronym Page Section 9 3 1 PBI Control Register PBCR on page 555 Section 9 3 2 PBI Status Register PBISR on page 555 Section 9 3 4 PBI Base Address Register 0 PBBAR0 on page 557 Sec...

Page 555: ...a rw na rw na rw na rv na rv na rv na rv na rw na rw na rw na rw na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rw na Attribute Legend RV Reserved PR Pres...

Page 556: ...ed the size of the memory window set in a limit register For a 1 Mbyte memory window only bit 20 through bit 31 of the base address from the PBI Base Address Register 0 PBBAR0 are relevant to the PBI...

Page 557: ...101 16 Data to Data wait states Others 20 Data to Data wait states Note By default the data to data wait states are 20 since it is the same as the address to data wait states 08 06 1112 Recovery Cycle...

Page 558: ...68 PBI Limit Register 0 PBLR0 Bit Default Description 31 12 FE000H Memory Window 0 Limit This value determines the memory block size required for the Memory Window 0 Defaults to an 32MB Peripheral Win...

Page 559: ...eld 010 4 Data to Data wait states 011 8 Data to Data wait states 100 12 Data to Data wait states 101 16 Data to Data wait states Others 20 Data to Data wait states Note By default data to data wait s...

Page 560: ...rmed Table 370 PBI Limit Register 1 PBLR1 Bit Default Description 31 12 00000H Memory Window 1 Limit Determines the memory block size required for the Memory Window 1 11 00 000H Reserved PCI IOP Attri...

Page 561: ...interface and the PCI X interface 15 12 00112 Pull Up Slew Rate Control PSLW 3 0 Tunes the slew rate of the p drivers of all the pins with the exception of the high speed serial interfaces the SDRAM...

Page 562: ...y divided by 2 012 3 1 Indicates that the Internal bus is running at the Core Frequency divided by 3 102 4 1 Indicates that the Internal bus is running at the Core Frequency divided by 4 112 Reserved...

Page 563: ...Reserved 16 x2 CLK_SRC_PCIE 15 x2 INTERFACE_SEL_PCIX 14 x2 CONTROLLER_ONLY 13 x2 LK_DN_RST_BYPASS 12 x2 PCIX_PULLUP 11 10 xx2 Reserved 09 07 xxx2 DEFSEL 2 0 06 x2 BOOT_WIDTH_8 Note This bit reflects...

Page 564: ...na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write RC Read Clear RO Rea...

Page 565: ...es an on chip programmable interrupt controller Requests for interrupt service come from many sources and are prioritized such that instruction execution is redirected only when an exception interrupt...

Page 566: ...ovement associated interrupts are fully demultiplexed into the ICU however In order to provide the executing software with the knowledge of interrupt source coprocessor mapped status registers describ...

Page 567: ...used to run normal non exception tasks that require a privileged processor mode 10 3 1 CPSR and SPSR All other processor state is held in status registers The current operating processor status is in...

Page 568: ...s user software must provide the following items in memory Exception Handler Routines Software handler to nest certain exceptions i e FIQ and IRQ These items are established in memory as part of the i...

Page 569: ...Each pin is a level detect input only These pins are internally synchronized These pins only act as interrupt inputs when they are unmasked in the INTCTL 3 0 registers These pins can also function as...

Page 570: ...errupt pin XINT4 GPIO 12 This is a bi directional pin This pin can act as an input XINT4 and drive the XINT4 input of the Interrupt Controller The Interrupt Controller Unit input XINT4 can be steered...

Page 571: ...Message Registers In this context a message is any 32 bit data value Message registers combine aspects of mailbox registers and doorbell registers Writes to the message registers may optionally cause...

Page 572: ...skable Inputs XINT 15 0 Note that when the 4138xx acts as an endpoint with the PCI X interface only twelve interrupt inputs XINT 15 4 are available instead of sixteen as the remaining four become outp...

Page 573: ...s When interrupt vector generation is enabled and there are multiple requests pending either in the FINTSRC 3 0 or the IINTSRC 3 0 registers the prioritization selects a highest priority active source...

Page 574: ...vely Note The 4138xx does not use all 128 possible sources ICU registers reside in Coprocessor 6 CP6 They may be accessed manipulated with the MCR MRC STC and LDC instructions The instruction CRn fiel...

Page 575: ...t Pending Intel XScale Core PMU Interrupt Pending Reserved Interrupt Pending Reserved Interrupt Pending Messaging Unit Interrupt Pending Reserved Peripheral Bus Interface Error ATUX Error ATUE Error I...

Page 576: ...SRC 3 0 registers depending on the value in INTSTR 3 0 To provide the best latency for high performance event driven activities the Application DMAs interrupts are fully demultiplexed into the interru...

Page 577: ...e inputs to the 4138xx Interrupt Controller are detailed in Table 379 Note The UART and I2C Bus Interface Unit interrupt sources are combined as a single interrupt and include both normal and error co...

Page 578: ...pending in the peripheral unit The appropriate FIQ or IRQ interrupt source bit is cleared by clearing the source of the interrupt at the internal peripheral Table 380 Error Interrupt Sources Unit Reg...

Page 579: ...generate two type of interrupts that are routed from the core as outputs and into the 4138xx ICU This mechanism allows these two core interrupts to be handled like any other peripheral interrupts by t...

Page 580: ...27 96 steered to IRQ IINTSRC0 0000 0000H All IRQ interrupts 31 0 inactive IINTSRC1 0000 0000H All IRQ interrupts 63 32 inactive IINTSRC2 0000 0000H All IRQ interrupts 95 64 inactive IINTSRC3 0000 0000...

Page 581: ...INTBASE Interrupt Base Register 2 Register 0 Reserved Reserved Register 1 INTSIZE Interrupt Size Register Register 2 IINTVEC IRQ Interrupt Vector Register Register 3 FINTVEC FIQ Interrupt Vector Regis...

Page 582: ...Priority Register 2 Register 2 IPR3 Interrupt Priority Register 3 Register 3 IPR4 Interrupt Priority Register 4 Register 4 IPR5 Interrupt Priority Register 5 Register 5 IPR6 Interrupt Priority Registe...

Page 583: ...s are used for a 512 Byte ISR memory range and the upper 16 bits for a 64 KByte ISR memory range etc Table 383 Interrupt Base Register INTBASE Bit Default Description 31 09 0000 00H Interrupt Base The...

Page 584: ...er INTSIZE Bit Default Description 31 04 0000000H Reserved 03 00 0H ISR Memory Range Size These bits define the size of the ISR memory range INTSIZE ISR Range Size ISR Size per Source 0 Disabled 1 512...

Page 585: ...bit 31 Before returning to User Mode from Interrupt Mode the software reads the IINTVEC register and process any lower priority IRQ sources that are active When there are no longer any active IRQ sou...

Page 586: ...bit 31 Before returning to User Mode from Interrupt Mode the software reads the FINTVEC register and process any lower priority FIQ sources that are active When there are no longer any active FIQ sou...

Page 587: ...rocessor Cache Interrupt Pending 17 02 Intel XScale Processor PMU Interrupt Pending 16 02 Peripheral Performance Monitor Interrupt Pending 15 02 ATU X Start BIST Interrupt Pending 14 02 ATU E Inbound...

Page 588: ...rupt Pending 18 08 0000H Reserved 07 02 XINT15 Interrupt Pending Source of this interrupt is the GPIO 7 pin 06 02 XINT14 Interrupt Pending Source of this interrupt is the GPIO 6 pin 05 02 XINT13 Inter...

Page 589: ...served 25 02 Reserved 24 02 Reserved 23 02 Reserved 22 02 Reserved 21 02 Reserved 20 02 Reserved 19 02 Reserved 18 02 Reserved 17 02 Reserved 16 02 Reserved 15 02 Reserved 14 02 Reserved 13 02 SRAM DM...

Page 590: ...4 02 ATUE Interrupt Message D Pending 13 02 ATUE Interrupt Message C Pending 12 02 ATUE Interrupt Message B Pending 11 02 ATUE Interrupt Message A Pending 10 08 02 Reserved 07 02 TPMI 0 Outbound Inter...

Page 591: ...Mask 0 Masked 1 Not Masked 25 02 XINT1 Interrupt Mask 0 Masked 1 Not Masked 24 02 XINT0 Interrupt Mask 0 Masked 1 Not Masked 23 19 02 Reserved 18 02 Intel XScale Processor Cache Interrupt Mask 0 Maske...

Page 592: ...t Masked 8 02 Timer 0 Interrupt Mask 0 Masked 1 Not Masked 7 02 Reserved 6 02 Watch Dog Timer Interrupt Mask 0 Masked 1 Not Masked 5 02 Reserved 4 02 Reserved 3 02 Reserved 2 02 Reserved 1 02 Reserved...

Page 593: ...22 02 ATU Configuration Register Write Interrupt Mask 0 Masked 1 Not Masked 21 02 Peripheral Bus Unit Error Interrupt Mask 0 Masked 1 Not Masked 20 02 UART 1 Interrupt Mask 0 Masked 1 Not Masked 19 0...

Page 594: ...ked 1 Not Masked 01 02 XINT9 Interrupt Mask Source of this interrupt is the GPIO 1 pin 0 Masked 1 Not Masked 00 02 XINT8 Interrupt Mask Source of this interrupt is the GPIO 0 pin 0 Masked 1 Not Masked...

Page 595: ...Internal Bus Bridge Error Interrupt Mask 0 Masked 1 Not Masked 29 14 02 Reserved 13 02 SRAM DMA Error Interrupt Mask 0 Masked 1 Not Masked 12 02 SRAM DMA Normal Interrupt Mask 0 Masked 1 Not Masked 11...

Page 596: ...terrupt Pending 0 Masked 1 Not Masked 14 02 ATUE Interrupt Message D Pending 0 Masked 1 Not Masked 13 02 ATUE Interrupt Message C Pending 0 Masked 1 Not Masked 12 02 ATUE Interrupt Message B Pending 0...

Page 597: ...ed 1 Not Masked 00 02 I2C Bus Interface 2 Interrupt Pending 0 Masked 1 Not Masked Table 394 Interrupt Control Register 3 INTCTL3 Sheet 2 of 2 Bit Default Description Memory Coprocessor Attributes Attr...

Page 598: ...rrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 26 02 XINT2 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 25 02...

Page 599: ...nternal FIQ 9 02 Timer 1 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 8 02 Timer 0 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt D...

Page 600: ...ATU Configuration Register Update Interrupt 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 21 02 Peripheral Bus Interface Unit Error Interrupt Steering 0 Interrupt Directed...

Page 601: ...rupt Directed to Internal FIQ 01 02 XINT9 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 00 02 XINT8 Interrupt Steering 0 Interrupt Directed to Internal I...

Page 602: ...Directed to Internal FIQ 30 02 South Internal Bus Bridge Error Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 29 14 02 Reserved 13 02 SRAM DMA Error Inter...

Page 603: ...Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 14 02 ATUE Interrupt Message D Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 13 02 ATUE Interrupt Me...

Page 604: ...T Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 00 02 I2C Bus Interface 2 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to...

Page 605: ...exception and unmasked by INTCTL0 27 02 XINT3 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0 1 Interrupting and steered to internal IRQ exception and unmask...

Page 606: ...0 11 02 I2C Bus Interface 1 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL0 10 0...

Page 607: ...ked by INTCTL1 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL1 23 02 ATU Error Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL1 1...

Page 608: ...ion or masked by INTCTL1 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL1 2 02 XINT10 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INT...

Page 609: ...ed by INTCTL2 30 02 South Internal Bus Bridge Error Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL2 1 Interrupting and steered to internal IRQ exception and...

Page 610: ...to internal IRQ exception and unmasked by INTCTL3 14 02 ATUE Interrupt Message D 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL3 1 Interrupting and steered to internal...

Page 611: ...ked by INTCTL3 01 02 ATU E Start BIST Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL3 1 Interrupting and steered to internal IRQ exception and unmasked by IN...

Page 612: ...ception and unmasked by INTCTL0 27 02 XINT3 Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0 1 Interrupting and steered to internal FIQ exception and unmasked...

Page 613: ...0 11 02 I2C Bus Interface 1 Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL0 10 0...

Page 614: ...on or masked by INTCTL1 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL1 21 02 Peripheral Bus Interface Unit Error Interrupt 0 Not Interrupting or Not steered to internal F...

Page 615: ...xception or masked by INTCTL1 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL1 1 02 XINT9 Interrupt Mask 0 Not Interrupting or Not steered to internal FIQ exception or mask...

Page 616: ...internal FIQ exception or masked by INTCTL2 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL2 29 14 02 Reserved 13 02 SRAM DMA Error 0 Not Interrupting or Not steered to in...

Page 617: ...nternal FIQ exception and unmasked by INTCTL3 14 02 ATUE Interrupt Message D 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3 1 Interrupting and steered to internal FIQ...

Page 618: ...ked by INTCTL3 01 02 ATU E Start BIST Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3 1 Interrupting and steered to internal FIQ exception and unmasked by IN...

Page 619: ...der bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table 407 Interrupt Priority Register 0 IPR0 Bit Default Description 31 30 002 ATU Start BIST Inter...

Page 620: ...cation Highest order bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table 408 Interrupt Priority Register 1 IPR1 Bit Default Description 31 30 002 XIN...

Page 621: ...ither FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priori...

Page 622: ...n bit location Highest order bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table 410 Interrupt Priority Register 3 IPR3 Bit Default Description 31 30...

Page 623: ...same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is first 002 High Priority 012 Medium High Priority 1...

Page 624: ...tively Note When multiple interrupts at the same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is first...

Page 625: ...pt Priority 29 28 002 ATUE Interrupt Message D Priority 27 26 002 ATUE Interrupt Message C Priority 25 24 002 ATUE Interrupt Message B Priority 23 22 002 ATUE Interrupt Message A Priority 21 10 002 Re...

Page 626: ...ly Note When multiple interrupts at the same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is first 002...

Page 627: ...access to CP6 use the Coprocessor Access Register Figure 71 shows a diagram of the timer functions See also Figure 72 for the Programmable Timer state diagram When enabled a timer decrements the user...

Page 628: ...period with the same 32 bit TCRx value Software can read or write the TCRx value whether the timer is running or stopped This lets the user monitor the count without using hardware interrupts When th...

Page 629: ...ed by the value E1E1 E1E1H to the WDT Control register When enabled the WDT is initialized with FFFF FFFFH and begin to decrement towards 0000 0000H The software is required periodically to write the...

Page 630: ...res any value specified for TMRx tc in a write request TMRx enable Timer Enable Bit 1 READ Bit is available 1 internal bus clock after executing a read instruction from TMRx WRITE Writing a 1 enables...

Page 631: ...ch timer interrupt can be selectively masked in the Interrupt Control INTCTL 1 0 registers Refer to the Interrupt Controller Unit Chapter for a description of interrupt controller operation After serv...

Page 632: ...TMRx pri 0 TMRx csel1 0 0 IPND tip 0 TMRx enable 1 TMRx reload user value TMRx pri user value TMRx csel1 0 user value TMRx reload user value TMRx pri user value TMRx csel1 0 user value TC 1 IPND tip 1...

Page 633: ...nt See Section 11 4 4 Timer Reload Register TRR0 1 on page 637 11 4 1 Power Up Reset Initialization Upon assertion of P_RST the timer registers are initialized to the values shown in Table 419 Table 4...

Page 634: ...clock 8 11 16 1 Timer Clock internal bus clock 16 03 02 Timer Register Privileged Write Control TMRx pri 0 Privileged and User Mode Write Enabled 1 Privileged Mode Only Write Enabled 02 02 Timer Auto...

Page 635: ...0 and Timer Auto Reload Enable TMRx reload bit 0 Hardware or software reset Refer to Section 17 2 Reset Overview on page 770 11 4 2 3 Bit 2 Timer Auto Reload Enable TMRx reload The TMRx reload bit det...

Page 636: ...put Clock Select TMRx csel1 0 User software programs the TMRx csel bits to select the Timer Clock TCLOCK frequency See Table 421 As shown in Figure 71 the internal bus clock is an input to the timer c...

Page 637: ...le range is from 1H to FFFF FFFFH Avoid programming a value of 0 as it may prevent TINTx from asserting continuously See Section 11 5 Uncommon TCRX and TRRX Conditions on page 640 for more information...

Page 638: ...og Timer detects a zero count in WDT After servicing the interrupt SW needs to write a 1 to this bit to clear the pending request Note that the Watchdog timer must be setup to generate an interrupt Re...

Page 639: ...alue By writing 1E1E 1E1EH followed by E1E1 E1E1H to this register software can enable the WDT and reset the count value to FFFF FFFFH When read this register returns the current value contained in th...

Page 640: ...r the Timer Reload Register to zero before enabling the timer Table 427 details the conditions and results when these conditions are set Table 427 Uncommon TMRx Control Bit Settings TRRx TCRx Bit 2 TM...

Page 641: ...ardware for an economical system to relay status and reliability information of the 4138xx to the system The SMBus Interface Unit is a peripheral device that resides on a 4138xx internal bus Data is t...

Page 642: ...ed with it The SMBus address is set upon P_RST by sampling the Peripheral Bus Interface Reset Strap inputs A 16 13 When the pins are sampled the resulting 4138xx address is stored in the Reset Strap S...

Page 643: ...master can then initiate a read sequence which returns the status of the internal read or write command and also the data in case of a read Each SMBus transaction has an 8 bit command driven by the m...

Page 644: ...gister PMMRBAR Refer to the Peripheral Registers Chapter for more details on the PMMRBAR register description The 4138xx ignores the upper 5 bits of ADDR2 and the entire ADDR3 fields when memory trans...

Page 645: ...compare the received address with their own and the target slave finds a match The next data bit from the initiator indicates the transfer direction A value of 1 indicates that the target needs to tr...

Page 646: ...0 during SMBCLK 1 A NACK requires SMBDAT 1 during SMBCLK 1 as shown below During a write cycle the 4138xx must drive an ACK after the address direction phase and after the data phase During a read cy...

Page 647: ...r writes The SMBus access is delayed by stretching the Table 430 SMBus Interface Registers for Configuration Space Access Register Name and Function CMD Command BYTCNT Byte Count ADDR3 Bus Numbera a T...

Page 648: ...configuration accesses from the SMBus port are initiated by writing to the Command register While a command is in progress all future writes or reads are NACKed by the 4138xx to avoid having registers...

Page 649: ...through an SMBus write s and later followed by an SMBus read to read the status and the read data For SMBus read transactions the last byte of data or the PEC byte when enabled is NACKed by the maste...

Page 650: ...ber 317805 001US Figure 79 DWORD Memory Read Protocol SMBus Block Write Block Read PEC Enabled Figure 80 DWORD Configuration Read Protocol SMBus Word Write Word Read PEC Enabled Figure 81 DWORD Config...

Page 651: ...Memory Read Protocol SMBus Word Write Byte Read PEC Enabled S 11X0_XXX W A Cmd 10110001 A Dest Mem A Add Offset 23 16 A PEC S 11X0_XXX W A Cmd 01110001 A Add Offset 15 8 A P S 11X0_XXX W A Cmd 1011000...

Page 652: ...ress For a Write DWord internal command the two least significant bits of the Register Number are ignored This is different from PCI where the byte enables are used to indicate the byte of interest Af...

Page 653: ...413812 I O Controllers in TPER Mode October 2007 Developer s Manual Order Number 317805 001US 653 SMBus Interface Unit Intel 413808 and 413812 Figure 88 DWORD Configuration Write Protocol SMBus Byte W...

Page 654: ...he command is set then the PEC byte is checked in the slave interface When the check indicates a failure then the slave NACKs the PEC packet and does not issue the command on the internal interface An...

Page 655: ...us Controller ADDR0 Register Number SM_ADDR0 on page 657 Section 440 SMBus Controller Data Register SM_DATA on page 658 Section 441 SMBus Controller Status Register SM_STS on page 658 Table 434 SMBus...

Page 656: ...gnored by 4138xx 12 4 4 SMBus Controller ADDR2 Register SM_ADDR2 This register should be programmed with the Device Number and Function Number of the desired configuration register The Status Register...

Page 657: ...bits bits 7 0 of the Register Number of the desired configuration register for 4 KByte configuration space The Status Register should be checked to make sure that there is not a command currently in p...

Page 658: ...32 bits of data are used The register number must be DWORD aligned The Status Register should be checked to make sure that there is not a command currently in progress before writing to this register...

Page 659: ...m the processor The processor can read the complete status of a UART at any time during the functional operation Available status information includes the type and condition of the transfer operations...

Page 660: ...by UART Receiver FIFO CTS input from modem controls UART transmitter Fully programmable serial interface characteristics 5 6 7 or 8 bit characters Even odd or no parity detection 1 1 1 2 or 2 stop bi...

Page 661: ...previous reading of the Modem Status register CTS has no effect on the transmitter The user can program the UART to interrupt the processor when DCTS changes state The programmer can then stall the o...

Page 662: ...by no line transition Figure 90 shows the NRZ coding of the data byte 8b 0100 1011 Note that the byte s LSB is transmitted first The unit is disabled upon reset and users need to enable the unit by se...

Page 663: ...When the transmitter FIFO and transmitter interrupt are enabled FCR 0 1 IER 1 1 transmit interrupts occur as follows When the Flow Control Register Transmitter Interrupt Level TIL bit FCR 3 is clear 0...

Page 664: ...and the timer is reset when a character is read from the Receiver FIFO When a time out Interrupt has not occurred the time out timer is reset after a new character is received or after the processor...

Page 665: ...w automating both CTS and RTS and half autoflow automating only CTS Full Autoflow is enabled by writing a 1 to bits 1 and 5 of the Modem Control register MCR Auto CTS Only mode is enabled by writing a...

Page 666: ...hen the remote transmitter s actual baud rate differs by more than one percent of its target The table method is more immune to such errors since the table rejects uncommon baud rates and rounds to th...

Page 667: ...ding it by any divisor from 1 to 216 1 The baud rate generator output frequency is 16 times the baud rate Two 8 bit registers store the divisor in a 16 bit binary format These Divisor Registers must b...

Page 668: ...8H X UxFCR UART x FIFO Control write only Base 0CH X UxLCR UART x Line Control R W Base 10H X UxMCR UART x Modem Control R W Base 14H X UxLSR UART x Line Status Read only Base 18H X UxMSR UART x Modem...

Page 669: ...Latch Low Byte R W 2304H 1 U0DLH UART 0 Divisor Latch High Byte R W 2324H X U0FOR UART 0 FIFO Occupancy Register R W 2328H X U0ABR UART 0 Autobaud Control Register R W 232CH X U0ACR UART 0 Autobaud Co...

Page 670: ...n FIFO mode writing to THR puts data to the top of the FIFO The data at the bottom of the FIFO is loaded to the Shift register when it is empty In eight bit Peripheral mode the 24 most significant bit...

Page 671: ...the unit is enabled 5 02 NRZ coding Enable NRZE 0 NRZ coding disabled 1 NRZ coding enabled 4 02 Receiver Time Out Interrupt Enable RTOIE 0 Receiver data Time out Interrupt disabled 1 Receiver data Ti...

Page 672: ...t Identification register IIR stores information indicating that a prioritized interrupt is pending and the source of that interrupt Table 450 UART x Interrupt Identification Register UxIIR Bit Defaul...

Page 673: ...vel or setting RESETRF bit in FCR register TOD 1 1 0 0 Second Highest Character Timeout indication FIFO Mode only At least 1 character is in receiver FIFO and there was no activity for a time period R...

Page 674: ...propriate bits are set in the IIR 00 1 byte or more in FIFO causes interrupt 01 8 bytes or more in FIFO causes interrupt 10 16 bytes or more in FIFO causes interrupt 11 32 bytes or more in FIFO causes...

Page 675: ...Note After the FIFO is cleared RESETRF is automatically reset to 0 0 no effect 1 The receiver FIFO is cleared FIFO counter set to 0 After clearing bit is automatically reset to 0 0 02 Transmit and Re...

Page 676: ...tter logic In FIFO mode wait for the transmitter to be idle TEMT 1 to set and clear the break bit 0 no effect on TXD output 1 forces TXD output to 0 space 5 02 Sticky Parity STKYP Can be used in multi...

Page 677: ...ter When STB is clear 0 one stop bit is generated in the transmitted data When STB is set 1 when a 5 bit word length is selected via WLS 1 0 then 1 and one half stop bits are generated When STB is set...

Page 678: ...put CTS is activated by MCR bit 1 instead of the modem control input A Break signal can also be transferred from the transmitter section to the receiver section in Loop Back mode When LOOP is set 1 th...

Page 679: ...bit of MCR is set auto RTS is enabled RTS behaves as follows Auto RTS disabled Autoflow works only with auto CTS Auto RTS enabled Autoflow works with both auto CTS and auto RTS 0 02 Reserved Table 454...

Page 680: ...ted only after the previous bytes are read and the erroneous byte is moved to the bottom of the FIFO Table 455 UART x Line Status Register UxLSR Sheet 1 of 3 Bit Default Description 31 8 00 0000h Rese...

Page 681: ...Break condition BI shows the Break condition for the character at the bottom of the FIFO not the most recent character received 0 No break signal has been received 1 Break signal has been received 3...

Page 682: ...overflow condition and reset when the processor reads the Line Status register 0 No overflow error Data has not been lost 1 Overflow error Receive data has been lost 0 02 Data Ready DR Set to a logic...

Page 683: ...upt Enable Register is set Table 457 UART x Modem Status Register UxMSR Bit Default Description 31 5 000 0000h Reserved 4 02 Clear to Send CTS This bit is the complement of the Clear to Send CTS input...

Page 684: ...Default Description 31 8 00 0000h Reserved 7 0 00h No effect on UART functionality P C I I O P A t t r i b u t e s A t t r i b u t e s 28 24 20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv n...

Page 685: ...h High Register UxDLH Bit Default Description 31 8 00 0000h Reserved 7 0 00h High byte compare value to generate baud rate P C I I O P A t t r i b u t e s A t t r i b u t e s 28 24 20 16 12 8 4 0 31 r...

Page 686: ...ted once for each byte of data written to the Receive FIFO and decremented once for each byte read Table 461 UART x FIFO Occupancy Register UxFOR Bit Default Description 31 7 000 0000h Reserved 6 0 00...

Page 687: ...llows the processor to read the Auto Baud Count register ACR and determine the baud rate using its own algorithm rather than using the UARTs 0 Software programs Divisor Latch Registers 1 UART Programs...

Page 688: ...the count value into the ACR The value is written regardless of the state of the auto baud UART program bit Table 463 UART x Auto Baud Count Register UxACR Bit Default Description 31 16 0000h Reserve...

Page 689: ...lave device residing on the I2 C bus The I2 C bus is a serial bus developed by Philips Corporation consisting of a two pin interface SDA is the data pin for input and output functions and SCL is the c...

Page 690: ...master addresses an EEPROM as a slave to receive data The 4138xx is a master transmitter and the EEPROM is a slave receiver When the 4138xx reads data the 4138xx is a master receiver and the EEPROM is...

Page 691: ...connection to the SCL line The I2 C bus serial operation uses an open drain wired AND bus structure which allows multiple devices to drive the bus lines and to communicate status about events such as...

Page 692: ...e Figure 92 shows a block diagram of the I2 C Bus Interface Unit and its interface to the internal bus The I2 C Bus Interface Unit consists of the two wire interface to the I2 C bus an 8 bit buffer fo...

Page 693: ...n 8 bit data buffer that receives a byte of data from the shift register interface of the I2 C bus on one side and parallel data from the 4138xx internal bus on the other side The serial shift registe...

Page 694: ...d in Section 14 3 5 Slave Operations on page 705 When the 4138xx wants to initiate a read or write on the I2 C bus the I2 C Bus Interface Unit transitions from the default Slave Receive mode to Master...

Page 695: ...on is sent by the I2C Bus Interface Unit This is used when multiple data bytes need to be transferred 0 1 STARTCondition and Repeated START The I2C Bus Interface Unit sends a START condition and trans...

Page 696: ...he ICR set to 002 is used in master transmit mode while the 4138xx is transmitting multiple data bytes see Figure 93 Software writes the data byte sets the IDBR Transmit Empty bit in the ISR and inter...

Page 697: ...nd the I2 C unit passes this onto the serial bus when the Transfer Byte bit in the ICR is set See Section 14 8 1 I2C Control Register x ICRx When the I2 C unit is in transmit mode master or slave 1 So...

Page 698: ...following the Ack and the addressed slave device transitions to slave transmit mode When a Nack is returned the I2 C unit aborts the transaction by automatically sending a STOP and setting the ISR bus...

Page 699: ...e bus error detected bit in the ISR is not set for a master receive mode Nack as required by the I2 C bus protocol The I2 C unit automatically transmits the Ack pulse based on the Ack Nack ICR bit aft...

Page 700: ...L Arbitration Each master on the I2 C bus generates its own clock on the SCL line for data transfers With masters generating their own clocks clocks with different frequencies may be connected to the...

Page 701: ...er addressing the 4138xx as a slave device the I2 C unit switches to slave receive mode and the original data in the I2 C data buffer register is overwritten Software is responsible for clearing the s...

Page 702: ...ormed after the target slave address and the R W bit are in the IDBR Intel XScale processor sets the START bit Intel XScale processor sets the Transfer Byte bit which initiates the start condition See...

Page 703: ...ing the STOP When the Ack Nack Status bit is set indicating Nack Transfer Byte bit is clear but the STOP bit is clear then the Intel XScale processor has two options 1 set the START bit write a new ta...

Page 704: ...t or Data Chaining see Figure 100 Figure 101 shows the wave forms of SDA and SCL for a complete data transfer Figure 99 Master Receiver Read from Slave Transmitter Figure 100 Master Receiver Read from...

Page 705: ...it An interrupt is signalled when enabled after the matching slave address is received and acknowledged Read one byte of I2C Data from the IDBR Slave receive only Data receive mode of I2C slave operat...

Page 706: ...er Read to Slave Transmitter Repeated START Master Transmitter Write to Slave Receiver Master to Slave Slave to Master START Slave Address R W 0 ACK Data Byte ACK Data Byte STOP N Bytes ACK Write ACK...

Page 707: ...C unit receives a general call address and the ICR General Call Disable bit is clear the I2 C unit Sets the ISR general call address detected bit Sets the ISR slave address detected bit Interrupts wh...

Page 708: ...for interrupt Read ISR Unit Busy clear Slave STOP Detected set 7 Clear interrupt by clearing Slave STOP Detected Interrupt bit 14 4 3 Read 2 Bytes as a Slave 1 Wait for Slave Address Detected interrup...

Page 709: ...e the access 5 Wait for Buffer empty interrupt When interrupt arrives Note Unit is sending STOP Read status register IDBR Transmit Empty set Unit busy set maybe R W bit clear Clear IDBR Transmit Empty...

Page 710: ...bit Clear STOP bit Set Transfer Byte bit to initiate the access 7 Wait for Buffer empty interrupt Read status register IDBR Transmit Empty set Unit busy set R W bit clear Clear IDBR Transmit Empty bit...

Page 711: ...nitiate the access 5 Wait for Buffer full interrupt Read status register IDBR Receive Full set Unit busy set R W bit Set Ack Nack bit Clear Clear IDBR Receive Full bit to clear the interrupt Read IDBR...

Page 712: ...7 712 Order Number 317805 001US 14 6 Glitch Suppression Logic The I2 C Bus Interface Unit has built in glitch suppression logic Glitches are suppressed according to 2 I2 C clock period For example wit...

Page 713: ...sible for ensuring the I2 C bus is idle when the unit is enabled after reset When directed to reset the I2 C unit returns to its default reset condition with the exception of the ISAR ISAR is not affe...

Page 714: ...ister titles x is 0 or 1 for unit 0 or 1 respectively They are all located within the peripheral memory mapped address space of the 4138xx Table 470 I2C Register Summary Section Register Name Acronym...

Page 715: ...for insuring that misplaced START and STOP conditions do not occur See Section 14 6 Glitch Suppression Logic on page 712 09 02 IDBR Receive Full Interrupt Enable 0 Disable interrupt 1 Enables I2C uni...

Page 716: ...2 02 Ack Nack Control defines the type of Ack pulse sent by the I2C unit when in master receive mode 0 The I2C unit sends an Ack pulse after receiving a data byte 1 The I2C unit sends a negative Ack N...

Page 717: ...transactions continue Software must insure that misplaced START and STOP conditions do not occur See Section 14 3 3 Arbitration on page 700 09 02 Slave Address Detected 0 No slave address detected 1...

Page 718: ...nit received or sent an Ack on the bus 1 The I2C unit received or sent a Nack This bit is used in slave transmit mode to determine when the byte transferred is the last one This bit is updated after e...

Page 719: ...eripherals that might exist in the system The ISAR is not affected by the 4138xx being reset The ISAR register default value is 00000002 Table 473 I2C Slave Address Register x ISARx Bit Default Descri...

Page 720: ...us is ready to transfer the next byte packet the I2 C Bus Interface Unit inserts wait states until the Intel XScale processor writes the IDBRx and sets the Transfer Byte bit When the I2 C Bus Interfac...

Page 721: ...Monitor Register x IBMRx Bit Default Description 31 02 0 Reserved 01 1 SCL Status This bit continuously reflects the value of the SCL pin 00 1 SDA Status This bit continuously reflects the value of t...

Page 722: ...ter x IMBCRx Bit Default Description 31 03 0 Reserved 02 0 SDA Control When bit 0 of the IMBCRx is set this bit controls the SDA pin 0 Pull Down the SDA pin 1 Do Not Pull Down the SDA pin 01 0 SCL Con...

Page 723: ...rnal interrupt inputs dedicated to the Intel XScale processor This feature is available on a per pin basis simply by programming the INTCTL 3 0 registers 15 1 2 General Purpose Outputs The output func...

Page 724: ...d through the internal memory bus Each is a 32 bit register and is memory mapped in the Intel XScale processor memory space The programmer interface to the General Purpose I O is through memory mapped...

Page 725: ...is enabled onto the GPIO 10 pin 09 12 GPIO9 Output Enable When clear bit 9 of the GPIO Output Data Register is enabled onto the GPIO 9 pin 08 12 GPIO8 Output Enable When clear bit 8 of the GPIO Outpu...

Page 726: ...12 pin 11 GPIO 11 during P_RST assertion GPIO11 Input Data This bit reflects the state of the GPIO 11 pin 10 GPIO 10 during P_RST assertion GPIO10 Input Data This bit reflects the state of the GPIO 1...

Page 727: ...ects the state of the GPIO 2 pin 01 GPIO 1 during P_RST assertion GPIO1 Input Data This bit reflects the state of the GPIO 1 pin 00 GPIO 0 during P_RST assertion GPIO0 Input Data This bit reflects the...

Page 728: ...the GPOE register is cleared 08 02 GPIO8 Output Data This bit value is driven on the GPIO 8 pin when bit 8 of the GPOE register is cleared 07 02 GPIO7 Output Data This bit value is driven on the GPIO...

Page 729: ...d registers Each counter has a corresponding command event status and data register The PMON unit implements eight counters Signals representing events from throughout the chip are routed to the PMON...

Page 730: ...317805 001US 16 2 1 Clock Counter Control When a counter is sampled the current value of the counter is latched into the corresponding data register The command event status and data registers are ac...

Page 731: ...o be counted by the PMON unit This includes clock crossing logic Two optional external pins allow for external visibility and control of the counters The output pin signals that one of the following c...

Page 732: ...PMON counters is not intended to be any wider than 32 bits This means that all registers are accessed one at a time All of the following examples assume starting with an idle system all counters stop...

Page 733: ...nterrupting the system and allowing the software to read data registers or do whatever else may be desired Example 7 Simple Counting This example demonstrates how to measure the number of times event...

Page 734: ...llows start stop sample and other commands to be executed as a result of other events happening Command Triggers refers to the ability of a command to be issued to the PMON unit and have it not be exe...

Page 735: ...events would no longer be counted Example 8 How many Event A s happen before the first Event B is detected This example demonstrates how to measure the number of times event A occurs before the first...

Page 736: ...ement of up to 2N 1 each clock tick where N is the number of counters available For example with 8 counters we could track an increment decrement of up to 128 27 each clock This would be done by assig...

Page 737: ...more useful when it is presented in a histogram Example 10 on page 738 outlines the command sequences required to generate such a histogram See the Head of Queue Histogram example in another section...

Page 738: ...vel depth of a particular queue No block diagram for this example Table 484 Queue Depth Histogram Example Opcode Target Counter Increment Event Decrement Event Trigger Event Write Threshold bucket siz...

Page 739: ...rtain event takes place An alternative way to represent the data in the preceding table is as follow For X 1 to 3 Write Threshold bucket size X into Data Register 0 Write Event Register 0 Increment Qu...

Page 740: ...l 413808 and 413812 PMON Unit Intel 413808 and 413812 I O Controllers in TPER Mode Developer s Manual October 2007 740 Order Number 317805 001US Figure 114 Block Diagram of HOQ Histogram Example B6304...

Page 741: ...tel 413808 and 413812 I O Controllers in TPER Mode October 2007 Developer s Manual Order Number 317805 001US 741 PMON Unit Intel 413808 and 413812 Figure 115 Waveforms of HOQ Histogram Example B6305 0...

Page 742: ...d produces identical queue behavior but the Counter 1 value called Condition Code Matches below differs due to having a different threshold value each time The condition code match values 10 8 4 3 fro...

Page 743: ...ock to produce the correct count Any events from different frequency domains must be preconditioned to assure count accuracy measured For these clock domain crossing signals 95 accuracy is sufficient...

Page 744: ...les are located in the PMON Feature Enable Register PMONEN on page 746 16 5 2 2 Interrupt Output An internal interrupt is delivered to the Interrupt Control Unit when Interrupts are enabled in the PMO...

Page 745: ...ge Offset Table 486 PMON Internal Bus Memory Mapped Register Range Offsets on page 745 to the Register Offset Table 487 PMON Register Summaries on page 745 For example the offset to PMMRBAR of the PMO...

Page 746: ...t Enable Enables 4138xx PMON unit generated interrupts PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv r...

Page 747: ...gisters are specified as a relative offset to a 512KB aligned global PMMR offset The default for the 512KB aligned offset is 0 FFD8 0000H defined by the PMMRBAR register See also Chapter 19 0 Peripher...

Page 748: ...STS2 02Ch PMON Data Register 2 PMON_DATA2 030h PMON Command Register 3 PMON_CMD3 034h PMON Event Register 3 PMON_EVR3 038h PMON Status Register 3 PMON_STS3 03Ch PMON Data Register 3 PMON_DATA3 040h PM...

Page 749: ...26 0b Overflow Underflow Indicator Enable OUIE 0 No indication provided when a counter overflow or underflow occurs except for setting the Overflow Underflow Indicator OUI status bit 1 When the overf...

Page 750: ...Than 101 Not Equal 110 Less Than or Equal 111 True always generate threshold event 20 0b Select ALL Counters SAC This bit controls how the opcode in bits 19 16 is applied to all counters The rest of t...

Page 751: ...g status register 0101 Restart The corresponding counter resets then starts counting again This is essentially a Reset Start command This functionality facilitates generating histograms by allowing an...

Page 752: ...mand to be re executed every time the trigger is detected Refer to the Event tables for valid values For the Stop Start and Reset opcodes re executing every time the trigger is detected is meaningless...

Page 753: ...n event from SAS SATA Port 1 etc 27 16 000h Decrement Event DE This field contains Event Selection Code ESC that the unit is required to detect before decrementing the associated counter This field is...

Page 754: ...are can poll this bit until it reads a 0 and then owns the usage of the corresponding counter This bit has no other effect on any PMON Counter registers and is only used as a semaphore among various i...

Page 755: ...ed 23 12 000h Reserved 11 4 TBD Clock Period CP This fixed point field is 5 3 format which allows representing clock periods from 0 125 ns 8 GHz to 31 875 ns a little over 31 MHz in 125 ps increments...

Page 756: ...on number of clock ticks or occurrences contained in PMON event counter n at time of sampling The register is programmed to contain the threshold value that is compared to the value in the event count...

Page 757: ...7 1 Null Event The Null Event is not an actual event When used as an increment or decrement event no action takes place When used as Command Trigger it causes command to be triggered immediately after...

Page 758: ...the threshold event triggers another counter to stop counting event AAAh 16 5 7 3 Threshold Events These are the outputs of the threshold comparators When the value in a data register is compared to...

Page 759: ...reserved 688 PCI Out bound Data Transferred N D Count equals number of 8_byte data cycles actual data transferred can be 1 to 8 bytes Data transferred for all cases where I O Processor is initiator of...

Page 760: ...ayer Packets Transmitted including Flow Control Updates 713 Total DLLPs Received N O Data Link Layer Packets Received including Flow Control Updates 714 71F Reserved 720 Inbound Data Transferred N OD...

Page 761: ...ary SourceSelect Value Port 0 Intel XScale core 0 1 Intel XScale core 1 2 Internal Bus Bridge 3 7 Reserved Table 503 North Internal Bus Initiator Events Event Selection Code Event SRC Type Comment 800...

Page 762: ...y Source Select Value Port 0 ATU E 1 ATU X 2 Internal Bus Bridge 3 Reserved 4 Reserved 5 7 Reserved Table 505 South Internal Bus Initiator Events Event Selection Code Event SRC Type Comment 880 SIB Ad...

Page 763: ...else Clock regions 3 4 and 6 are driven off the core PLL and are pseudo synchronous to each other There are asynchronous boundaries between regions 1 3 regions 2 3 6 3 and between regions 7 3 Figure...

Page 764: ...The analog front end for this region generates the 2 5 GHz clock used for the serial PCI Express interface as well as a 250 MHz clock used by the transaction layer In addition to the locally generated...

Page 765: ...y Initializationa a 81348 does not support PCI X 533Mhz P_PCIXCAP P_MODE2 P_M66EN PCIXM1_100 PCIXM2_100 PCI Bus Mode PCI Bus Frequency ATUX PCSR 19 16 0 11VCC b b A in table indicates value is a don t...

Page 766: ...CI X Initialization Pattern1 PERR DEVSEL STOP TRDY ATUX PCSR 19 16 Mode Clock Frequency MHz Minimum Maximum Deasserted Deasserted Deasserted Deasserted 1111 PCI 33 16 33 1111 PCI 66 33 66 Deasserted D...

Page 767: ..._CLKOUT to drive the ATUX PCI interface These clock outputs are can only be used when the PCI Express reference clock REFCLK is used as the primary chip clock and the ATUX is enabled and configured to...

Page 768: ...it specified in region 3 This region operates at a fixed 66 MHz and depending on the frequency of region 3 may be an asynchronous boundary 17 1 1 5 Clocking Region 5 Region 5 obtains its input clock f...

Page 769: ...en REFCLKN REFCLKP are used the I O processor can generate the PCI output clocks These pins then provide the PCI clocks to devices on the PCI bus The P_CLKOUT and P_CLKO 3 0 outputs are enabled when t...

Page 770: ...et is not applicable when the PCI Express interface is disabled A subset of straps are sampled as described in Section 17 5 Reset Strapping Options PCI Express Loopback When operating as an endpoint a...

Page 771: ...XScale processor to imitate a reset to another core in the system including itself 17 2 3 Secondary Bus Reset When operating as a root complex or central resource the following secondary bus resets ap...

Page 772: ...press Hot Reset The PCI Express specification defines an in band reset sequence that is used to reset the link and downstream components The Root Complex communicates the fact that it is entering and...

Page 773: ...at the trailing edge of the fundamental resets and control the default value of the Core Processor Reset bits in function 0 When invoked via the strap software should clear the Core Processor Reset b...

Page 774: ...CI bus traffic before initiating the Internal Bus Reset 1 Disable the ATU from either claiming or initiating new transactions by clearing the Bus Master Enable and the Memory Enable in the ATU Command...

Page 775: ...e data it has been requested to read Once terminated by the ATUX or the target the ATUX no longer requests the PCI bus In PCI X mode the ATUX allows any outstanding split completions due to prior outs...

Page 776: ...CI Express link is a point to point interface so no precautions need to be taken before resetting the link End Point Mode No affect on ATUE logic All ATUX Configuration Registers retain their current...

Page 777: ...PCI_RST signal while the P_RST pin can be tied to the system power good signal When the sticky bit functionality is not required the WARM_RST pin should not be used and must be tied to Vcc When the P...

Page 778: ...age Port Allocation CONTROLLER_ONLY 1 DF_SEL 2 0 Intel 413808 and 413812 I O Controllers in TPER Mode Function 0 ATU Function 1 TPMI1 000 8 n a 001 Reserved 010 011 100 101 110 111 Table 517 Non TPER...

Page 779: ...d at the deassertion of the fundamental reset All the straps are sampled at the trailing edge of P_RST and WARM_RST however a subset of straps are sampled for other resets P_RST and WARM_RST Sample al...

Page 780: ...strap is latched at the trailing edge of reset and reflected in Core 1 Processor Reset bit in function 0 See Section 17 2 7 Intel XScale Processor Reset Mechanism for more details When asserted the as...

Page 781: ...or 1 64 Bit PCI X Bus Default mode HS_SM Hot Swap Startup Mode 0 Hot Swap Mode Enabled Requires pull down resistor 1 Hot Swap Mode Disabled default mode SMB_A5 SMB_A3 SMB_A2 SMB_A1 SMBUS Address maps...

Page 782: ...18 1 Overview This chapter summarizes testability and configuration features incorporated in the Intel 413808 and 413812 I O Controllers in TPER Mode 4138xx The 4138xx test and control logic is based...

Page 783: ...TDO TAP controller Instruction register Group of test data registers Each of these is described in more detail below Figure 120 shows a generic diagram for logic conforming to the IEEE 1149 1 test st...

Page 784: ...on the rising edge of TCK Data shifted from TDI through a register to TDO appears non inverted at TDO after a number of rising and falling edges of TCK determined by the length of the instruction or t...

Page 785: ...test logic instruction register data registers etc occur on either rising or falling edge of TCK as show in Figure 121 See the description of each state to learn which For greater detail on the state...

Page 786: ...he controller remains in this state as long as TMS is held low In the Run Test Idle state activity in selected test logic occurs only when certain instructions are present For example the RUNBIST inst...

Page 787: ...he Pause DR state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO All test data registers selected by the curr...

Page 788: ...register is connected between TDI and TDO and shifts data one bit position nearer to its serial output on each rising edge of TCK All test data registers selected by the current instruction retain the...

Page 789: ...controller enters the Update IR state and the scanning process terminates When TMS is held low during the next rising edge of TCK the controller re enters the Shift IR state 18 2 2 16 Update IR State...

Page 790: ...state machine outputs are decoded to select and control the test data register selected by that instruction Upon latching all actions caused by any previous instructions must terminate On activation o...

Page 791: ...without interfering with that normal operation The instruction causes Boundary Scan register cells associated with outputs to sample the value being driven by or to the processor When the TAP controll...

Page 792: ...path between TDI and TDO This path can be selected when no test operation is being performed While the Bypass Register is selected data is transferred from TDI to TDO without inversion 18 2 3 5 Devic...

Page 793: ...troller continues to operate with the bypass register connected between TDI and TDO The part may have other settings as long as they do not interfere with these two requirements Following the use of H...

Page 794: ...are specific to the 4138xx only They support the Each of these peripherals fully describe the independent functionality of the registers control and usage Control and status registers for the Intel X...

Page 795: ...or Register Interface Registers may be accessed manipulated through the CCR interface with the MCR MRC STC and LDC instructions The CRn field of the instruction denotes the register number to be acces...

Page 796: ...ated at addresses 0 FFD8 0000H through 0 FFDF FFFFH Do not change the default address of the PMMR block The Messaging Unit occupies 8 KBytes of space and is located at addresses 0 FF00 0000H through 0...

Page 797: ...FFD 0000H 0 FFFB 0000H 0 FFE0 0000H 0 FFFE 0000H 0 FFD4 0000H 0 FFD2 0000H 0 FFCF C000H ATU E Outbound I O Translation Window ATU X Outbound I O Translation Window Default Default Range 0 FFF0 0000H R...

Page 798: ...tel XScale Microarchitecture Developer s Manual which describes various methods of fencing memory accesses Table 522 PMMR Base Address Register PMMRBAR Default Value Register Absolute Address PMMRBAR...

Page 799: ...Registers PCI Attributes Reserved 4 6000H through 4 6FFFH 4 KBytes Not Claimed by any Unit 4 7000H through 4 7FFFH 4 KBytes PCI Function 0 Configuration Registers Local Attributes 4 8000H through 4 8...

Page 800: ...med by any Unit 6 C000H through 6 DFFFH 8 KBytes Not Claimed by any Unit 6 E000H through 6 FFFFH 8 KBytes Reserved 7 0000H through 7 1FFFH 8 KBytes Reserved 7 2000H through 7 3FFFH 8 KBytes Reserved 7...

Page 801: ...ress PMMRBAR PBI Base Address Offset Register Offset Note Additionally GPIO 8 0 I O pad control registers are located in the I O Pad Control Unit registers block Table 524 PBI Base Address Offset Unit...

Page 802: ...MMRBAR System Controller 1640H Table 527 System Controller Unit Register Description Name Register Size in Bits Internal Bus Address Offset Relative to SC Base Address Offset Internal Bus Arbitration...

Page 803: ...erface 2100H Other Units 2180H Table 531 I O Pad Control Unit Unit Register Description Name Register Size in Bits Internal Bus Address Offset RelativetoI OPad Control Base Address Offset Peripheral B...

Page 804: ...1 2340H Table 533 UART Register Description Name Register Size in Bits Internal Bus Address Offset Relative to UARTx Base Address Offset UART x Receive Buffer Register Read Only DLAB 0 32 00H UART x...

Page 805: ...rnal Bus Address PMMRBAR I2 C Base Address Offset Register Offset Table 534 GPIO Offset Unit GPIO Base Address Offset Relative to PMMRBAR GPIO 2480H Table 535 GPIO Register Description Name Register S...

Page 806: ...32 010H Inbound Message Register IMR1 32 014H Outbound Message Register OMR0 32 018H Outbound Message Register OMR1 32 01CH Inbound Doorbell Register IDR 32 020H Inbound Interrupt Status Register IISR...

Page 807: ...MU MSI X Table Message Vector Control Register 3 M_MT_MVCR3 32 103C MU MSI X Table Message Address Register 4 M_MT_MAR4 32 1040 MU MSI X Table Message Upper Address Register 4 M_MT_MUAR4 32 1044 MU M...

Page 808: ...PMON_CMD1 32 10H PMON Event Register 1 PMON_EVR1 32 14H PMON Status Register 1 PMON_STS1 32 18H PMON DATA Register 1 PMON_DATA1 32 1CH PMON Command Register 2 PMON_CMD2 32 20H PMON Event Register 2 PM...

Page 809: ...associated with each unit and its Base Address Offset are detailed in Table 542 PCI Function MMR Locations Table 542 PCI Function MMR Locations PCI Function Number CONTROLLER_ONLY 0 has priority over...

Page 810: ...uration Space Base Address Offset on page 810 to the Register Offset Table 544 Address Translation Unit Registers ATUX on page 811 For example when INTERFACE_SEL_PCIX and CONTROLLER_ONLY are bothasser...

Page 811: ...Register ASVIR 16 02CH ATU Subsystem ID Register ASIR 16 02EH Expansion ROM Base Address Register ERBAR 32 030H ATU Capabilities Pointer Register ATU_Cap_Ptr 8 034H Reserved 24 035H Reserved 32 038H...

Page 812: ...MSI X_Table_Offset 32 0B4H MSI X Pending Bit Array Offset Register MSI X_PBA_Offset 32 0B8H MU MSI X Control Register x MMCRx 32 0BCH Reserved x 0C0H through 0CFH PCI X Capability Identifier Register...

Page 813: ...er 32 bit Memory Window Translate Value Register 3 OUMWTVR3 32 324H Reserved 32 328H Reserved 32 32CH Outbound Configuration Cycle Address Register OCCAR 32 330H Outbound Configuration Cycle Data Regi...

Page 814: ...the Register Offset Table 546 Address Translation Unit Registers ATUE on page 815 For example when INTERFACE_SEL_PCIX and CONTROLLER_ONLY are both asserted the offset to PMMRBAR of the ATU Command Reg...

Page 815: ...CH ATU Subsystem ID Register ASIR 16 02EH Expansion ROM Base Address Register ERBAR 32 030H ATU Capabilities Pointer Register ATU_Cap_Ptr 8 034H Reserved 24 035H Reserved 32 038H ATU Interrupt Line Re...

Page 816: ...t 32 0B4H MSI X Pending Bit Array Offset Register MSI X_PBA_Offset 32 0B8H MU MSI X Control Register x MMCRx 32 0BCH Reserved x 0C0H through 0CFH PCI Express Capability Identifier Register PCIE_CAPID...

Page 817: ...23 32 x24 200H through 25CH Reserved x 260H through 2FFH Outbound I O Base Address Register OIOBAR 32 300H Outbound I O Window Translate Value Register OIOWTVR 32 304H Outbound Upper Memory Window Ba...

Page 818: ...ayload Register OVMPR 32 370H Reserved x 374H through 37FH PCI Interface Error Control and Status Register PIE_CSR 32 380H PCI Interface Error Status PIE_STS 32 384H PCI Interface Error Mask PIE_MSK 3...

Page 819: ...erence Manual provides for a total of 16 coprocessors each of which can contain up to 256 32 bit registers For completeness the coprocessor space reserved by the ARM Architecture Reference Manual is s...

Page 820: ...Pending Register 1 Register 9 Inbound MSI Interrupt Pending Register 2 Register 10 Inbound MSI Interrupt Pending Register 3 Register 11 Undefined Register 12 through Register 15 I n t e r r u p t C o...

Page 821: ...Register 3 Register 3 Undefined Register 4 15 FIQ Interrupt Source Register 0 7 Register 0 FIQ Interrupt Source Register 1 Register 1 FIQ Interrupt Source Register 2 Register 2 FIQ Interrupt Source R...

Page 822: ...a c e U n it L2 Cache and BIU Error Logging Register CP7 2 Register 0 L2 Cache and BIU Error Lower Address Register Register 1 L2 Cache and BIU Error Upper Address Register Register 2 Undefined Regist...

Page 823: ...iary Control Registers Register 1 Translation Table Base Register Register 2 Domain Access Control Register Register 3 Undefined Register 4 Fault Status Register Register 5 Fault Address Register Regi...

Page 824: ...Intel 413808 and 413812 Peripheral Registers Intel 413808 and 413812 I O Controllers in TPER Mode Developer s Manual October 2007 824 Order Number 317805 001US...

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