Intel
®
413808 and 413812—Clocking and Reset
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
764
Order Number: 317805-001US
17.1.1
Clocking Theory of Operation
Each region within the 81348 contains different clocking requirements. These
requirements are summarized in the following sections.
17.1.1.1 Clocking Region 1 (PCI Express)
Region 1 obtains its input clock from the PCI Express reference clock The
/-
differential input supplies a 100 MHz clock for normal operation on the PCI Express
interface. The analog front end for this region generates the 2.5 GHz clock used for the
serial PCI Express interface as well as a 250 MHz clock used by the transaction layer. In
addition to the locally generated clocks, region 1 utilizes the internal bus clock
generated by the core PLL to interface to the internal bus (region 3).
Also contains a 25 MHz clock used by the power management logic.
17.1.1.2 Clocking Region 2 (PCI)
Region 2 obtains its input clock from the PCI bus clock connected to the input pin
P_CLKIN
. 81348 supports an input frequency of 33 MHz, 66 MHz, 100 MHz, and
133 MHz for normal operation on the PCI interface. Additionally region 2 utilizes the
internal bus clock generated by the core PLL to interface to the internal bus (region 3).
