Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
292
Order Number: 317805-001US
The first byte at the Extended Configuration Offset 90H is the VPD Capability Identifier
Register (
Section 3.17.44
). This identifies this Extended Configuration Header space as
the type defined by the PCI Local Bus Specification, Revision 2.3.
Following the Capability Identifier Register is the single byte Next Item Pointer Register
(
Section 3.17.47
) which indicates the configuration offset of an additional Extended
Capabilities Header, when supported. In the ATU, the Next Item Pointer Register is set
to 00H indicating that there are no additional Extended Capabilities Headers supported
in the ATUs configuration space.
The following sections describe the ATU and Expansion ROM configuration registers.
Configuration space consists of 8, 16, 24, and 32-bit registers arranged in a predefined
format. Each register is described in functionality, access type (read/write, read/clear,
read only) and reset default condition.
See
Section 1.6, “Terminology and Conventions” on page 48
for a description of
reserved, read only, and read/clear. All registers adhere to the definitions found in the
PCI Local Bus Specification, Revision 2.3 unless otherwise noted.
The PCI register number for each register is given in
Table 141
.
Note:
Each configuration register’s access type is individually defined for PCI configuration
accesses. Some PCI read-only configuration registers have read/write capability from
the 4138xx core CPU. See also
Chapter 19.0, “Peripheral Registers”
.
