Intel
®
413808 and 413812—SMBus Interface Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
648
Order Number: 317805-001US
clock until such time that the data is delivered. Note that per the SMBus specification,
this cannot be longer than 25 ms. To set up an internal access, the command register
write is followed by four ADDR byte writes. Depending on the type of access, these four
bytes indicate either the Bus number, Device, Function, Extended Register Offset, and
Register Offset, or the Memory-mapped region selected and the address within the
region. The configuration type access utilizes the traditional bus number, device,
function, and register offset; but in addition, also uses an extended register offset
which expands the addressable register space from 256 bytes to 4 Kbytes. The
memory-mapped type access redefines these bytes to be a memory-mapped region
selection byte, a filler byte which today is all zeroes, and then the memory address
within the region. Refer to the earlier tables, which display this information. Note that
the filler byte is today not utilized but enforces that both types of accesses have the
same number of address bytes, and allows for future expansion.
The Command Register (CMD) indicates the type and size of transfer. All configuration
accesses from the SMBus port are initiated by writing to the Command register. While a
command is in progress, all future writes or reads are NACKed by the 4138xx to avoid
having registers overwritten while in use. There are two command size fields to allow
for more flexibility on how the data payload is transferred, both internally and
externally. Refer to the Command Register for more details on the size supported. The
command register also provides a begin bit and an end bit. These two bits support the
breaking of the SMBus transactions up into smaller transfers, by defining the start and
finish of an overall transfer.
The 4138xx SMBus interface supports byte, word, or block transfer sizes. A byte size
indicates that the data payload is transferred one byte at a time per SMBus transaction.
A word size indicates that the data payload is transferred one word (2 bytes) at a time
in a single SMBus transaction. A block size allows a variable size data payload to be
transferred in a single SMBus transaction. When a block transfer is to be performed an
8-bit byte-count field follows the command register. This byte-count field provides the
4138xx target with the expected number of bytes to anticipate from the SMBus Master.
For a block read transaction, the 4138xx returns a byte-count value to the master
when returning read data. This provides the master with a byte-count to anticipate.
Note that on 4138xx, the block transfer size is limited to only a maximum of four bytes.
