Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
234
Order Number: 317805-001US
3.3
ATU Address Translation
The ATU allows PCI Express requesters to initiate transactions to the 4138xx internal
bus and allows the Intel XScale
®
processor to initiate transactions in the PCI Express
domain.
The ATU implements an address windowing scheme to determine which addresses to
claim and translate to the destination bus.
• The address windowing mechanism for inbound translation is described in
Section
3.3.1.1, “Inbound Address Translation” on page 237
.
• The address windowing mechanism for outbound translation is described in
Section
3.3.2, “Outbound Transactions” on page 244
and
Section 3.3.3, “Outbound Write
Transaction” on page 251
.
The ATU has the ability to accept up to eight inbound PCI Express Non Posted Read
(memory read, configuration read, and I/O read) transactions, one inbound Non Posted
Write (configuration write and I/O write) transaction, and16 inbound PCI Express
Posted (memory write and message) transactions simultaneously.
As a PCI Express end point, the ATU must advertise infinite credits for Completion
Headers and Completion Data. As a requester the ATU never requests more read data
than it has room for in its Inbound Completion queues (ICPLHQ and ICPLDQ).
Also, the ATU has the ability to accept up to eight outbound Non Posted (internal bus
read, configuration, and I/O) transactions and four outbound Posted (internal bus write
and message) transactions simultaneously.
Of the 8 outbound Non Posted transactions, 4 is actively requesting data while the
other 4 remains pending until one of the earlier active transactions is completed. Each
active outbound read request may be fragmented into sub-requests based on the
MAX_READ_REQUEST_SIZE parameter programmed in the
“PCI Express Device Control
Register - PE_DCTL” on page 344
. The fragmentation may result in as many as 8
sub-requests per active read transaction. The ATU tracks a maximum of 32 outstanding
non posted transactions at once. Completions for these sub-requests can return out of
order on the PCI Express interface but they are returned in order on the internal bus.
Outbound memory writes and completions may be fragmented into smaller
transactions based on the setting of the MAX_PAYLOAD_SIZE in the
“PCI Express
Device Control Register - PE_DCTL” on page 344
.
Outbound completions obeys the minimum fragmentation limit of 128Bytes.
Refer to
Figure 23
and
Section 3.8
for details of the ATU queue architecture.
As a master on the internal bus, the ATU never requests more read data than it has
room for in the Outbound Completion queues (OCPLHQ and OCPLDQ).
Inbound memory writes are fragmented on 1KB address aligned boundaries before
issuing on the internal bus. Since the maximum payload size supported by the PCI
Express interface is 512 Bytes each transactions are fragmented into a maximum of
two internal bus transactions. Additionally, write combining does not occur.
Inbound completions are attempted on the internal bus with the same payload size as
was received from PCI Express. In most instances the PCI Express completion size is
64B or 128B. The PCI express completions may be combined into larger completion
transactions on the internal bus.
Inbound memory read requests are fragmented into 1KB aligned sub-requests.
Completions for these sub-requests can be received out of order on the internal bus
and is returned in order on the PCI Express interface.
