Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
513
SRAM Memory Controller—Intel
®
413808 and 413812
8.3
Theory of Operation
The 4138xx SRAM memory controller translates transactions from the north internal
bus into the protocol supported by the SRAM memory subsystem.
8.3.1
Functional Block
The SRAM memory controller logically comprises the blocks illustrated in
Figure 56
. The
SMCU supports a separate read and write port.
The SMCU provides ports for direct SRAM access. Each device connects to the SMCU
using a separate read port and write port. Each port provides a 128-bit data path. The
ports are described in the next sub-sections:
8.3.1.1
North Internal Bus Ports
The North Internal Bus Port provides the 4138xx processor core access to the SRAM
Memory Controller. This North Internal Bus Port allows core transactions targeting the
SRAM via the North Internal Bus bus to pass directly to the SRAM.
Figure 56. Intel
®
413808 and 413812 I/O Controllers in TPER Mode SRAM Memory
Controller Block Diagram
SRAM Memory
Array
North Internal Bus
North IB
Address
Decode
SRAM
Control
North IB Port
Transaction
Queue
SRAM MCU
1 Read Port
and
1 Write Port
Intel
XScale®
Processor
Intel
XScale®
Configuration
Registers
Processor
B6268-01
