8. JTAG and Boundary Scan > Configuration Register Access (Revision C)
CPS-1848 User Manual
188
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
A 58-bit instruction is shifted in through TDI with bit 0 being applied first and bit 57 applied last. As the new instruction is shifted
in through TDI, the previous instruction and its status are shifted out through TDO with bit 0 emerging first and bit 57 emerging
last.
8.7.1
Inter-Command Delay
In order to do a JTAG register access operation, the TAP Controller must first be loaded with the Configuration Register Access
instruction by shifting 0xA into the Instruction Register (see
).
Once the TAP Controller is in the Configuration Register Access state, commands can be shifted in, and their results shifted
out, as shown in
. This figure shows the standard JTAG state machine that is implemented in the CPS-1848’s TAP
Controller. Each inter-state arc is annotated with the TMS input value needed to traverse that arc.
The CPS-1848 JTAG register access mechanism allows only one command to be in progress at a time (see
). For
example, JTAG register access command B cannot be started until JTAG register access command A has completed. To allow
sufficient time for command A to finish before starting command B, the agent that applies JTAG register access commands
must hold the TAP Controller in the JTAG Run-Test/Idle state for a minimum amount of time between register access
commands.
35:34
CMD
2
0b0x = NOP command. NOP commands allow shifting out of the results of the
previous command without starting a new command.
0b10 = Read
0b11 = Write
57:36
ADDR
22
This is the most significant 22 bits of the 24-bit register address offset.
S-RIO configuration registers are 4-byte aligned and therefore the lower 2 bits
of the offset are always 0.
Table 73: JTAG Configuration Register Access Command and Status Instruction (Continued)
Bits
Field Name
Size
Description
