IDT CPS-1848, User Manual, Page: 189 / 450

8. JTAG and Boundary Scan > Configuration Register Access (Revision C)
CPS-1848 User Manual 189 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
Figure 44: Inter-Command Delay
Superimposed on the state machine are the sequence of states required for register access command A, the inter-command
delay, and register access command B. The blue line shows the sequence of states needed to apply command A. The orange
line shows the sequence of states needed to apply command B. The red line shows the inter-command delay that must be
applied after Command A before command B can be started.
Table 74 summarizes the minimum inter-command delay requirement.
Table 74: Minimum Inter-Command Delay
Core Clock Rate (MHz)
Minimum Inter-command Delay in
Run-Test/Idle (Microseconds)
312.5 1
156.25 2
Test Logic Reset
Select-DR
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
0
1
0
1 1
1
0
0
1
0
1
1
1 0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
1
0 1
1
Run-Test/Idle
Command A
Command B
Delay