IDT CPS-1848, User Manual

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3. RapidIO Lanes > Port and Lane Initialization Sequence
CPS-1848 User Manual 77 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
The CPS-1848 supports lane lengths up to those specified by the RapidIO medium-run PHY standard without link partner
transmit emphasis or DFE. The transmit emphasis settings of the CPS-1848 and the link partner may need to be adjusted for
channels longer than medium run. Depending on the electrical characteristics of the channel, CPS-1848 receiver DFE may
also be necessary for channels longer than medium run.
3.4.1.1 CPS-1848 Transmitter Emphasis Control
The RapidIO specification defines a transmitter emphasis function that is controlled by two filter coefficients called the Pre and
Post taps. The CPS-1848 transmitter emphasis coefficients can be changed by writing them directly.
3.4.1.1.1 Register Control of CPS-1848 Transmit Emphasis
The CPS-1848 transmit emphasis is controlled by each lane using commands written to the POS1_CMD and NEG1_CMD
fields in the
Lane {0..47} Status 3 CSR . The supported commands include pre and post tap value increases and decreases, as
well as changes to configured reset and preset tap values. The reset and preset values for each of the two pre-emphasis taps
are configured through writes to the
Lane {0..47} Status 2 CSR .
The output waveform has three parameters that can be modified by writing the desired value to the register field:
• NEG1_TAP[4:0] (
Lane {0..47} Status 3 CSR ) – This corresponds to the Pre tap.
• TX_AMP_CTL[5:0] ( Lane {0..47} Control Register )
• POS1_TAP[5:0] ( Lane {0..47} Status 3 CSR ) – This corresponds to the Post tap.
The adjustment of NEG1_TAP and POS1_TAP tap change the spectral content of the waveform with the intent of improving
the eye shape at the receiver. The TX_AMP_CTL control adjusts the signal amplitude to allow the signal amplitude to be
reduced for short links, or to be increased on lossy and long links. The NEG1_TAP and POS1_TAP selections are applied only
to sequences of two or more bits of the same value. The TX_AMP_CTL control is applied to all bits on the lane. The following
figures show the relationship between the waveform voltage change imposed by the tap setting (in dB volts) and the register
(DAC, or Digital Analog Converter) value programmed in the NEG1_TAP field of the corresponding
Lane {0..47} Status 3 CSR .
The following waveform shows the effects on the waveform for NEG1_TAP settings of zero (top), 0b01111 (middle), and
0b11111 (bottom). The POS1_TAP is set to 0 and the TX_AMP_CTL value is set to 52 (default).