IDT CPS-1848, User Manual

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10. Registers > Global Device Configuration Registers
CPS-1848 User Manual 368 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
10.14.17 Device Reset and Control Register
Register Name: DEVICE_RESET_CTL
Reset Value: 0x0000_0000 Register Offset: 0xF20300
Bits 0 1 2 3 4 5 6 7
00:07 DO_RESET RESET_TY
PE
PLL_SEL
08:15 PLL_SEL PORT_SEL
16:23 PORT_SEL
24:31 PORT_SEL
Bits Name Description Type
Reset
Value
0 DO_RESET 1 = Reset the structures defined in the PORT_SEL field if
RESET_TYPE is 0. If RESET_TYPE is 1 then a soft reset of the
entire device is triggered. WO 0
1 RESET_TYPE This register can be used for two types of resets:
0 = Reset the local facilities that are defined in this register (that
is, specific ports and PLLs) is performed. PLL_SEL and
PORT_SEL are active for this setting.
1 = Reset all device-level digital logic (global reset) except for the
configuration registers is performed. This includes all lanes,
ports, the switch fabric, the maintenance block, the I2C Interface
and the JTAG logic. PORT_SEL is not active for this reset, but
PLL_SEL indicates that PLL resets can also be triggered with this
reset.
Note: This reset requires the CPS-1848 to be quiescent (it is not
transmitting or receiving packets). RW 0
2:13 PLL_SEL When DO_RESET is 1, all PLLs represented by bits in this field
that are set to 1 are reset.
Bit 2 = PLL 11
Bit 3 = PLL 10
...
Bit 13 = PLL 0
Note: The main use of this field is to initiate resets to specific
PLLs when a modification to the PLL_DIV_SEL field in the
PLL
{0..11} Control 1 Register is made that requires a reset to a
specific PLL. PORT_SEL is expected to be used in conjunction
with the PLL resets selected in this field.
RW 0