IDT CPS-1848, User Manual

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10. Registers > Error Management Extensions Block Registers
CPS-1848 User Manual 258 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
10.7.11 Port {0..17} Attributes Capture CSR
For base address information, see Port Error Management Register Base Addresses .
Register Name: PORT_{0..17}_ATTR_CAPT_CSR
Reset Value: 0x0000_00000 Register Offset: 0x (0x40 * port_num)
Bits 0 1 2 3 4 5 6 7
00:07 INFO_TYPE ERR_TYPE
08:15 Reserved
16:23 Reserved IMP_DEP
24:31 IMP_DEP Reserved VALID
Bits Name Description Type
Reset
Value
0:2 INFO_TYPE Type of logged information
0b000 = Packet
0b001 = Reserved
0b010 = Short control symbol (only error capture register 0 is
valid)
0b011 = Long control symbol (only error capture registers 0 and 1
are valid)
0b100 = Implementation-specific data is logged
0b101 = Reserved
0b110 = Undefined S-bit error
0b111 = Reserved RW 0b000
3:7 ERR_TYPE This is an encoded value representing the bit number in the Port
{0..17} Error Detect CSR , which indicates the error that was
captured.
The actual bit numbering of the encoded value is 31 decimal
minus “error detect bit position.”
RW 0x00
8:22 Reserved Reserved RO 0
23:27 IMP_DEP Only valid if ERR_TYPE is set to represent bit 0 in the Port {0..17}
Error Detect CSR ; that is, ERR_TYPE = 0b11111. This field
contains the bit number in the Port {0..17} Implementation
Specific Error Detect Register which represents the error that was
captured.
RW 0
28:30 Reserved Reserved RO 0
31 VALID 1 = The Capture registers contain valid information. For
information on what is captured for which event, see
Physical
Layer Events .
RW 0