2. RapidIO Ports > Packet Transfer Validation and Debug
CPS-1848 User Manual
62
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
2.11 Packet Transfer Validation and Debug
2.11.1
Overview
The performance counter registers that are described in the following sections should be the first tool to use when validating
and debugging the transfer of packets.
2.11.1.1
Receive Port Counters
For a stream of receive packets, assuming Packet Accepted has been sent for all received packets, no new packets have been
received, and no error recovery has occurred, the following relationship exists:
•
Port {0..17} VC0 Acknowledgements Transmitted Counter Register
=
Port {0..17} VC0 Received Packets Dropped Counter
Port {0..17} VC0 Packets Received Counter Register
•
Port {0..17} VC0 Packets Received Counter Register
– Increments when EOP is detected, and the packet is not retried, not
dropped due to no-route, and not invalid (bad TTYPE, maintenance packet too long).
•
Port {0..17} VC0 Received Packets Dropped Counter Register
– Increments when a packet is dropped due to no-route
and/or invalid TT field is detected.
•
Port {0..17} VC0 Acknowledgements Transmitted Counter Register
– Increments when packet-accepted CS is sent.
•
Port {0..17} Not Acknowledgements Transmitted Counter Register
– Increments when packet-not-accepted CS is sent. No
relation to other counters (NACK’d packets are not counted as received or dropped).
•
Port {0..17} VC0 Retry Symbols Transmitted Counter Register
– Increments when a retry CS is sent. No relation to other
counters (retried packets are not counted as received nor dropped).
2.11.1.2
Transmit Port Counters
For a stream of transmit packets, assuming all outstanding packet acknowledgments (PA, NACK, RTRY) have been received,
and no error recovery occurs, the following relationship exists:
•
Port {0..17} VC0 Packets Transmitted Counter Register
Port {0..17} VC0 Acknowledgements Received Counter Register
+
Port {0..17} Not Acknowledgements Received Counter Register
Port {0..17} VC0 Retry Symbols Received Counter
•
Port {0..17} VC0 Packets Transmitted Counter Register
– Increments when a packet is transmitted all the way to EOP,
including retransmissions.
•
Port {0..17} VC0 Acknowledgements Received Counter Register
– Increments when a packet-accepted CS is received.
•
Port {0..17} Not Acknowledgements Received Counter Register
– Increments when a packet-not-accepted CS, with cause
other than “lack of resources,” is received.
•
Port {0..17} VC0 Retry Symbols Received Counter Register
– Increments when a retry CS, packet-not-accepted CS with
cause “lack of resources,” is received.
The Start Port can revert to normal operation without resetting the CPS-1848. The End Port, however,
cannot revert to normal operation until a software or hardware device reset. The End Port can receive
only the first 25 packets.
Except for the counters captured below, all other counters are “informational only” and should not be
relied on to be completely accurate or consistent.
