8. JTAG and Boundary Scan > Initialization and Reset
CPS-1848 User Manual
185
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
8.5
Initialization and Reset
At power-up, the TRST_N signal must be asserted LOW to bring the TAP Controller up in a known, reset state. As per the
IEEE 1149.1 Specification, the user can alternatively hold the TMS pin high while clocking TCK five times (minimum) to reset
the controller. To deactivate JTAG, tie TRST_N low so that the TAP Controller remains in a known state at all times. All of the
other JTAG input pins are internally biased such that by leaving them unconnected they are automatically disabled. Note that
JTAG inputs are OK to float because they have leakers (as required by the IEEE 1149.1 Specification).
8.6
Configuration Register Access (Revision A/B)
In addition to the S-RIO and I
2
C ports, the TAP port provides another interface to access any of the CPS-1848’s configuration
registers. Through the use of the “Configuration Register Access” opcode, writes and reads to any register are possible. The
same JTAG instruction is used for both writes and reads of the Configuration Register space. Bit zero of the TDI data stream
defines whether or not the command is a write or a read.
The system reset sequence for the CPS-1848 must be completed before a JTAG Configuration
Register Access operation is started.
Table 72: Configuration Registers
Bits
Field Name
Size
Description
[0]
jtag_config_wr_n
1
0 = Write configuration register
1 = Read configuration register
[22:1]
jtag_config_addr
22
Starting address of the memory-mapped configuration register
[54:23]
jtag_config_data
32
Reads: Data shifted out (one 32-bit word per read) is read from the
configuration register at address jtag_config_addr.
Writes: Data shifted in (one 32-bit word per write) is written to the
configuration register at address jtag_config_addr.
The CPS-1848’s JTAG functionality does not support register access when it is part of a chain of JTAG
devices. The CPS-1848 must be the only device on the JTAG bus when its registers are accessed
using JTAG. Register access, however, can still be performed from the RapidIO or I2C interfaces.
