CPS-1848 User Manual
23
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
1. Device
Overview
This chapter provides an overview of the CPS-1848’s capabilities. Topics discussed include the following:
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1.1
Device Description
The CPS-1848 is a low-latency, 18 port, 48 lane, Gen2 RapidIO switch that supports a peak sustained throughput of 240 Gbps
(see
). The switch is ideal for interconnecting Gen1 and Gen2 RapidIO endpoints, including microprocessors, DSPs,
FPGAs, ASICs, and bridges. The CPS-1848 supports port widths of 1x, 2x, and 4x, and lane speeds of 1.25, 2.5, 3.125, 5.0,
and 6.25 Gbaud. The switch supports the RapidIO long run specification (100 cm of FR4 with two connectors), so it is ideal for
backplane and interchassis switching applications, as well as on-board interconnect.
All RapidIO packets that are compliant to the RapidIO Specification (Rev. 2.1), Part 6: LP-Serial Physical Layer Specification
and Part 3: Common Transport Specification, are accepted and routed by the CPS-1848. Packets are scheduled based on
priority in accordance with the RapidIO specification. This includes FType 9 data streaming packets described in the RapidIO
specification, Part 10: Data Streaming Specification.
RapidIO switching supports standard RapidIO routing functionality, including unicast and up to 40 multicast groups. The
CPS-1848 exceeds the RapidIO Specification (Rev. 2.1) to support broadcast routing of packets and an innovative hierarchical
routing scheme that supports all 64K 16-bit destIDs. The CPS-1848 supports the CRF bit to enable flow control based on eight
separate priorities. The CPS-1848’s queue aging function also ensures that high priority traffic does not starve low priority
traffic under congestion. In addition, the CPS-1848 supports a powerful packet trace and filter functionality, and a separate
routing path for maintenance packets.
The CPS-1848 is designed to support fault tolerant systems. RapidIO Specification (Rev. 2.1), Part 8 “Error Management
Extensions” support is supplemented by additional implementation specific event detection and notification functionality. Fault
isolation support includes the RapidIO standard “leaky bucket” port failure handling, as well as implementation specific
functions. Hot swap is fully supported through the use of “per port”' reset capability.
In addition to the RapidIO Interface, the CPS-1848 supports JTAG 1149.1 and 1149.6 test and register access interface, as
well as I2C master and slave access.
1.2
Key Features
• RapidIO Interfaces
— Up to 18 RapidIO Specification (Rev. 2.1) compliant ports
— Up to 48 RapidIO Specification (Rev. 2.1) compliant full duplex lanes, supporting 4x, 2x, and 1x ports
— 1.25, 2.5, 3.125, 5, or 6.25 Gbaud lane rates selectable for each port
