8. JTAG and Boundary Scan > Test Instructions
CPS-1848 User Manual
184
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
8.3
Test Instructions
8.4
Device ID Register
The JTAG Device ID register length is 32 bits wide. The Capture Data Register value is the Device ID.
The JTAG Device ID register is mapped to the DEVICE field in the
. The CPS-1848 provides no correlation
between the value in this register and the device’s I
2
C address. There is no provision to read the I
2
C address from the TAP
port.
The 11-bit JTAG Vendor ID is 0xB3 where the MSB is 1 (the code itself uses an ODD parity bit in the 8th bit). As per the IEEE
1149.1 Specification, the first 7 bits of the Vendor ID will be the first 7 bits of the EIA/JEP106 code “discarding the parity bit.”
Thus, the JTAG IDCODE read from the TAP port is 0x33.
Table 71: Test Instructions
IR Code [3:0]
Instruction
Comments
0x0
Ex_Test
Implemented per IEEE 1149.1-2001
0x1
Sample/Preload
Implemented per IEEE 1149.1-2001
0x2
ID Code
Implemented per IEEE 1149.1-2001
Device ID = 0x374
0x3
High Z
Implemented per IEEE 1149.1-2001
0x4
Clamp
Implemented per IEEE 1149.1-2001
0x5
Ex_Test Pulse
Implemented per IEEE 1149.6
0x6
Ex_Test Train
Implemented per IEEE 1149.6
0x7
Reserved
-
0x8
Reserved
-
0x9
Reserved
-
0xA
Configuration Register
Access
IDT-specific Read and Write Access to Configuration Register space
0xB
Reserved
-
0xC
Reserved
-
0xD
Reserved
-
0xE
Reserved
-
0xF
Bypass
Implemented per IEEE 1149.1-2001
