IDT 89HPES48T12G2, User Manual

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IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PES48T12G2 User Manual 15 - 18 April 5, 2013
9:4 NLW RO HWINIT Negotiated Link Width. This field indicates the negotiated width of
the link.
00 0001b - x1
00 0010b - x2
00 0100b - x4
00 1000b - x8
00 1100b - x12
01 0000b - x16
10 0000b - x32
When the MAXLNKWDTH field in the PCIELCAP register selects a
width not supported by the port, the value of this field corresponds
to the setting of the MAXLNKWDTH field, regardless of the actual
negotiated link width.
When the MAXLNKWDTH field in the PCIELCAP register selects a
width supported by the port, but the link is unable to train, the value
in this field is set to 0x0.
10 Reserved RO 0x0 Reserved field.
11 LTRAIN RO 0x0 Link Training. When set, this bit indicates that link training is in
progress.
This bit is set when the Physical Layer LTSSM is in Configuration
or Recovery State, or when 0x1 is written to LRET bit in the
PCIELCTL register but Link training has not yet begun.
Hardware clears this bit when LTSSM exits Configuration/ Recov-
ery State.
This bit is only valid when the port operates in ‘Downstream Switch
Port’ mode. Else, this bit always has a value of 0x0.
12 SCLK RWL HWINIT Slot Clock Configuration. When set, this bit indicates that the
port uses the same physical reference clock used by its link partner
(i.e., common-clock configuration). The initial value of this field
depends on the port’s clocking mode. Refer to Table 4.1 for further
details.
13 DLLLA RO 0x0 Data Link Layer Link Active. This bit indicates the status for the
data link control and management state machine.
0x0 - (not_active) Data link layer not active state
0x1 - (active) Data link layer active state
This bit must never be set by hardware if the DLLLA bit in the
PCIELCAP register is cleared.
14 LBWSTS RW1C 0x0 Link Bandwidth Management Status. This bit is set to indicate
that either of the following have occurred without the link transition-
ing through the DL_Down state.
A link retraining initiated by setting the LRET bit in the PCIELCTL
register has completed.
The PHY has autonomously changed link speed or width to
attempt to correct unreliable link operation either through an
LTSSM time-out or a higher level process.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was not
indicated as an autonomous change.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in an upstream port.
Bit
Field
Field
Name
Type
Default
Value
Description