IDT 89HPES48T12G2, User Manual

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IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PES48T12G2 User Manual 15 - 61 April 5, 2013
IERRORSEV - Internal Error Reporting Severity (0x48C)
14 EFBCTLDBE RW 0x0
SWSticky
EFB Control Double Bit Error. When this bit is set, the corre-
sponding error bit in the IERRORSTS register is masked from
reporting an internal error to the AER Capability Structure. This bit
does not affect the state of the corresponding bit in the IER-
RORSTS register.
15 E2EPE RW 0x0
SWSticky
End-to-End Data Path Parity Error. When this bit is set, the cor-
responding error bit in the IERRORSTS register is masked from
reporting an internal error to the AER Capability Structure. This bit
does not affect the state of the corresponding bit in the IER-
RORSTS register.
16 ULD RW 0x0
SWSticky
Unreliable Link Detected. When this bit is set, the corresponding
error bit in the IERRORSTS register is masked from reporting an
internal error to the AER Capability Structure. This bit does not
affect the state of the corresponding bit in the IERRORSTS regis-
ter.
17 RBCTLSBE RW 0x0
SWSticky
Replay Buffer Control Single Bit Error. When this bit is set, the
corresponding error bit in the IERRORSTS register is masked from
reporting an internal error to the AER Capability Structure. This bit
does not affect the state of the corresponding bit in the IER-
RORSTS register.
18 RBCTLDBE RW 0x0
SWSticky
Replay Buffer Control Double Bit Error. When this bit is set, the
corresponding error bit in the IERRORSTS register is masked from
reporting an internal error to the AER Capability Structure. This bit
does not affect the state of the corresponding bit in the IER-
RORSTS register.
31:19 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 IFBPTLPTO RW 0x1
SWSticky
IFB Posted TLP Time-Out. This bit controls how an unmasked
error of the corresponding type is reported. When this bit is set and
the corresponding status bit is set and unmasked, then the error is
reported as an uncorrectable internal error. When this bit is cleared
and the corresponding status bit is set and unmasked, then the
error is reported as an correctable internal error.
1 IFBNPTLPTO RW 0x0
SWSticky
IFB Non-Posted TLP Time-Out. This bit controls how an unmasked
error of the corresponding type is reported. When this bit is set and
the corresponding status bit is set and unmasked, then the error is
reported as an uncorrectable internal error. When this bit is cleared
and the corresponding status bit is set and unmasked, then the
error is reported as an correctable internal error.
2 IFBCPTLPTO RW 0x0
SWSticky
IFB Completion TLP Time-Out. This bit controls how an unmasked
error of the corresponding type is reported. When this bit is set and
the corresponding status bit is set and unmasked, then the error is
reported as an uncorrectable internal error. When this bit is cleared
and the corresponding status bit is set and unmasked, then the
error is reported as an correctable internal error.
3 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description