IDT 89HPES48T12G2, User Manual

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IDT Switch Configuration and Status Registers
PES48T12G2 User Manual 16 - 7 April 5, 2013
11:10 TX_EQ_3DBG2 RW 0x1
SWSticky
Transmit Equalization for Full Swing Mode with -3.5dB in
Gen2.
This field controls the transmit equalization in Gen 2 data
rate, when the SDE field in the associated port’s PCIELCTL2 regis-
ter is set to -3.5 dB de-emphasis.
This field controls the transmit equalization for the lane(s) selected
by the Lane Select (LANESEL[3:0]) field in the SerDes Control
(S[x]CTL) register.This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL register).
Valid values for this field are 0x0 to 0x3.
13:12 TX_EQ_6DBG2 RW 0x1
SWSticky
Transmit Equalization for Full Swing Mode with -6.0dB in
Gen2.
This field controls the transmit equalization in Gen 2 data
rate, when the SDE field in the associated port’s PCIELCTL2 regis-
ter is set to -6.0 dB de-emphasis.
This field controls the transmit equalization for the lane(s) selected
by the Lane Select (LANESEL[3:0]) field in the SerDes Control
(S[x]CTL) register.This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL register).
Valid values for this field are 0x0 to 0x3.
15:14 TX_EQ_LS RW 0x0
SWSticky
Transmit Equalization for Low Swing Mode. This field controls
the transmit equalization when the associated port operates in low-
swing mode (i.e., the LSE bit in the port’s SERDESCFG register is
set to 0x1), for both Gen 1 and Gen 2 data rates.
This field controls the transmit equalization for the lane(s) selected
by the Lane Select (LANESEL[3:0]) field in the SerDes Control
(S[x]CTL) register.This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL register).
Valid values for this field are 0x0 to 0x3.
17:16 TX_SLEW_G1 RW 0x2
SWSticky
Transmit Slew Control in Gen1. This field controls the output
driver’s slew rate at Gen1 data-rate, for the lane(s) selected by the
Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL)
register.
This value is SWSticky for all lanes (i.e., even those not selected
by the LANESEL field in the S[x]CTL register)
0x0 - 48 ps
0x1 - 50 ps
0x2 - 60 ps
0x3 - 89 ps
20:18 TX_FSLEW_G1 RW 0x0
SWSticky
Transmit Driver Fine Slew Adjustment in Gen1. This field allows
fine adjustment of the output driver’s slew rate at Gen 1 data-rate,
for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in
the SerDes Control (S[x]CTL) register.
This value is SWSticky for all lanes (i.e., even those not selected
by the LANESEL field in the S[x]CTL register).
22:21 TX_SLEW_G2 RW 0x0
SWSticky
Transmit Slew Control in Gen2. This field controls the output
driver’s slew rate at Gen2 data-rate, for the lane(s) selected by the
Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL)
register.
This value is SWSticky for all lanes (i.e., even those not selected
by the LANESEL field in the S[x]CTL register)
0x0 - 48 ps
0x1 - 50 ps
0x2 - 60 ps
0x3 - 89 ps
Bit
Field
Field
Name
Type
Default
Value
Description