IDT 89HPES48T12G2, User Manual

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IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PES48T12G2 User Manual 15 - 22 April 5, 2013
PCIESSTS - PCI Express Slot Status (0x05A)
9:8 PIC RW HWINIT Power Indicator Control. When read, this register returns the cur-
rent state of the Power Indicator. Writing to this register sets the
indicator.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
This field is always zero if the PWRIP bit is cleared in the PCIES-
CAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
0x0 - (reserved) Reserved
0x1 - (on) On
0x2 - (blink) Blink
0x3 - (off) Off
This field has no effect on the upstream port.
10 PCC RW HWINIT Power Controller Control. When read, this register returns the
current state of the power applied to the slot. Writing to this register
sets the power state of the slot.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
0x0 -(on) Power on
0x1 -(off) Power off
11 EIC RW HWINIT Electromechanical Interlock Control. This field always returns a
value of zero when read. If an electromechanical interlock is imple-
mented, a write of a one to this field causes the state of the inter-
lock to toggle and a write of a zero has no effect.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
12 DLLLASCE RW HWINIT Data Link Layer Link Active State Change Enable. This bit
when set enables generation of a Hot-Plug interrupt or wake-up
event on a data link layer active field state change.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
15:13 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 ABP RW1C 0x0 Attention Button Pressed. Set when the attention button is
pressed.
1 PFD RW1C 0x0 Power Fault Detected. Set when the Power Controller detects a
power fault.
Bit
Field
Field
Name
Type
Default
Value
Description