IDT 89HPES48T12G2, User Manual

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IDT Power Management
PES48T12G2 User Manual 10 - 2 April 5, 2013
Notes
Figure 10.1 PES48T12G2 Power Management State Transition Diagram
PCI-to-PCI bridge Functions have the following behavior when in the D3
hot
power management state.
– A bridge accepts, processes and completes all type 0 configuration read and write requests.
– Accepts and processes all message requests that target the bridge.
– All requests received by the bridge on the primary interface, except as noted above, are treated
as unsupported requests (UR).
– Any error message resulting from the receipt of a TLP is reported in the same manner as when
the bridge is not in D3
hot
(e.g, generation of an ERR_NONFATAL message to the root).
• This requires transitioning the link to the L0 state when error reporting is enabled and the link is
not in L0.
– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no
error message is generated).
– All completions that target the bridge are treated as unexpected completions (UC).
– Completions flowing in either direction through the bridge are routed as normal. This behavior of
the bridge does not differ from that of the bridge when it is in the D0 power management state.
From State To State Description
any D0 Uninitialized Switch reset (any type).
D0 Uninitialized D0 Active Function configured by software
D0 Active D3
hot
The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to the D3
hot
state.
D3
hot
D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power
Management Control and Status (PMCSR) register is written with the
value that corresponds to D0 state.
D3
hott
D3
cold
Power is removed from the device.
Table 10.1 PES48T12G2 Power Management State Transition Diagram
D0
Uninitialized
D0
Active
D3
hot
Reset
D3
cold