IDT 89HPES48T12G2, User Manual

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IDT PES48T12G2 Device Overview
PES48T12G2 User Manual 1 - 8 April 5, 2013
Notes
PE07TP[3:0]
PE07TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PE08RP[3:0]
PE08RN[3:0] I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive
pairs for port 8.
PE08TP[3:0]
PE08TN[3:0] O PCI Express Port 8 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 8.
PE09RP[3:0]
PE09RN[3:0] I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive
pairs for port 9. When port 8 is merged with port 9, these signals become
port 8 receive pairs for lanes 4 through 7.
PE09TP[3:0]
PE09TN[3:0] O PCI Express Port 9 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 9. When port 8 is merged with port 9, these signals
become port 8 transmit pairs for lanes 4 through 7.
PE12RP[3:0]
PE12RN[3:0] I PCI Express Port 12 Serial Data Receive. Differential PCI Express
receive pairs for port 12.
PE12TP[3:0]
PE12TN[3:0] O PCI Express Port 12 Serial Data Transmit. Differential PCI Express
transmit pairs for port 12.
PE13RP[3:0]
PE13RN[3:0] I PCI Express Port 13 Serial Data Receive. Differential PCI Express
receive pairs for port 13. When port 12 is merged with port 13, these sig-
nals become port 12 receive pairs for lanes 4 through 7.
PE13TP[3:0]
PE13TN[3:0] O PCI Express Port 13 Serial Data Transmit. Differential PCI Express
transmit pairs for port 13. When port 12 is merged with port 13, these sig-
nals become port 12 transmit pairs for lanes 4 through 7.
Signal Type Name/Description
GCLKN[1:0]
GCLKP[1:0] I Global Reference Clock. Differential reference clock input pair. This clock
is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
Table 1.5 Reference Clock Pins
Signal Type Name/Description
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 1.6 SMBus Interface Pins
Signal Type Name/Description
Table 1.4 PCI Express Interface Pins (Part 2 of 2)