IDT 89HPES48T12G2, User Manual, Page: 78 / 276

IDT Link Operation
PES48T12G2 User Manual 6 - 14 April 5, 2013
Notes
L1 ASPM Entry Rejection Timer
When enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, PES48T12G2
downstream ports respond to link partner requests to enter the L1 ASPM state. In order to enter the L1
ASPM link state, a downstream device (i.e., endpoint) sends continuous PM_Active_State_Request_L1
DLLPs to its link partner (i.e., a downstream switch port). This process continues until the downstream
device receives an acceptance or rejection from its link partner.
A PES48T12G2 downstream port can choose to accept or reject the request, depending on a variety of
conditions (refer to section L1 Entry Conditions on page 6-13). When accepting a request, the
PES48T12G2 downstream port sends continuous PM_Request_Ack DLLPs until the downstream device
receives these and sends an electrical idle ordered set, effectively placing the link in L1 state.
When rejecting a request, the PES48T12G2 downstream port sends a single PM_Active_State_Nak
TLP. The downstream device, upon reception of this TLP, should place its transmitter into the L0s state, and
exit this state prior to sending a new L1 ASPM entry request. Optionally, the downstream device may keep
the link in L0 state, in which case it must wait at least 10 µs before sending a new L1 ASPM entry request.
Some endpoint devices do not meet the required 10 µs gap between consecutive L1 ASPM entry
requests. A live-lock situation can develop in the following scenario:
– The Endpoint sends continuous PM_Active_State_Request_L1 DLLPs to the downstream port of
a switch.
– The switch receives the request but decides to reject (i.e., due to a TLP already queued for trans-
mission on this link). The switch sends a PM_Active_State_Nak TLP to the endpoint device.
– The endpoint device notices the rejection, waits an amount of time (i.e., 8 µs) and resumes trans-
mission of PM_Active_State_Request_L1 DLLPs.
– The switch receives PM_Active_State_Request_L1 DLLPs, but does not recognize them as a
new L1 ASPM entry request, since there was a violation of the 10 µs gap between L1 ASPM entry
requests.
– The switch does not respond with an acceptance or rejection. Therefore, the endpoint keeps
waiting for an acceptance or rejection. A live-lock condition develops.
To avoid this live-lock condition, PES48T12G2 downstream ports allow programmability of a timer that
checks for the 10 µs gap between L1 ASPM entry requests. There is a timer per port. The Minimum Time
between L1 Entry Requests (MTL1ER) field in the L1 ASPM Rejection Timer Control (Px_L1ASPMRTC)
register may be programmed for this purpose.
This timer may be programmed from the nano-second range (i.e., 100 ns) up to the micro-second range
(i.e., 64 µs). By default, the timer is set to 9.5 µs (refer to the Implementation note in Section 5.4.1.2 of the
PCI Express 2.0 spec).
Normally, this timer starts its count after the switch downstream port issues an L1 ASPM rejection (i.e.,
PM_Active_State_Nak TLP), without checking activity on the link. The PES48T12G2 also provides an
option to start the timer after the downstream port issues an L1 ASPM rejection (i.e., PM_Active_State_Nak
TLP) and no activity is detected on the receive-lanes. The Timer Start Control (TSCTL) in the L1ASPMRTC
register controls this behavior. This feature allows the PES48T12G2 downstream ports to enter L1 ASPM
with a variety of endpoints, even those that don’t meet the 10 µs gap between subsequent L1 ASPM entry
requests.
Link Status
Associated with each PES48T12G2 port is a Port Link Up (PxLINKUPN) status output and a Port
Activity (PxACTIVEN) status output. These outputs are provided on an I/O expander. The PxLINKUPN and
PxACTIVEN status outputs may be used to provide a visual indication of system state and activity or for
debug. The PxLINKUPN output is asserted when the port’s data link layer is up (i.e., when the LTSSM is in
the L0, L0s, L1 or recovery states). When the data link layer is down, this output is negated.
The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined message, is trans-
mitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it remains
asserted for at least 200 ms. Since an I/O expander output may change no more frequently than once every
40 ms, this translates into five I/O expander update periods.