IDT 89HPES48T12G2, User Manual

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IDT PES48T12G2 Device Overview
PES48T12G2 User Manual 1 - 7 April 5, 2013
Notes
Pin Description
The following tables list the functions of the pins provided on the PES48T12G2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the
positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the
differential pair.
Signal Type Name/Description
PE00RP[3:0]
PE00RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE00TP[3:0]
PE00TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE01RP[3:0]
PE01RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PE01TP[3:0]
PE01TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PE02RP[3:0]
PE02RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE02TP[3:0]
PE02TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE03RP[3:0]
PE03RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PE03TP[3:0]
PE03TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PE04RP[3:0]
PE04RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE04TP[3:0]
PE04TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE05RP[3:0]
PE05RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PE05TP[3:0]
PE05TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PE06RP[3:0]
PE06RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE06TP[3:0]
PE06TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PE07RP[3:0]
PE07RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
Table 1.4 PCI Express Interface Pins (Part 1 of 2)