IDT 89HPES48T12G2, User Manual, Page: 252 / 276

IDT Switch Configuration and Status Registers
PES48T12G2 User Manual 16 - 8 April 5, 2013
25:23 TX_FSLEW_G2 RW 0x0
SWSticky
Transmit Driver Fine Slew Adjustment in Gen2. This field allows
fine adjustment of the output driver’s slew rate at Gen 2 data-rate,
for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in
the SerDes Control (S[x]CTL) register.
This value is SWSticky for all lanes (i.e., even those not selected
by the LANESEL field in the S[x]CTL register).
26 TX_SLEW_C RW 0x0
SWSticky
Transmit Slew Control Disable.
When set, the slew control fields in this register (TX_SLEW_G1/2
and TX_FSLEW_G1/2) are disabled and the SerDes transmitter
uses its maximum slew rate setting.
28:27 TX_AMPBOOST RW 0x1
SWSticky
Transmit Driver Amplitude Boost. This field increases the trans-
mitter driver’s differential swing for the lane(s) selected by the Lane
Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL) regis-
ter.
Valid settings are 0x0 to 0x3, where 0x0 selects no amplitude
boost and 0x3 selects the highest amount of boost. Each increas-
ing setting boosts the amplitude by ~5% over the previous setting.
Increasing this setting will also increase the power consumed by
the affected lanes. Each increasing setting increases power con-
sumption by ~2% over the previous setting.
This value is SWSticky for all lanes (i.e., even those not selected
by the LANESEL field in the S[x]CTL register).
31:29 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description