IDT 89HPES48T12G2, User Manual

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IDT Register Organization
PES48T12G2 User Manual 14 - 10 April 5, 2013
Notes
IDT Proprietary Port Specific Registers
This section outlines the address range 0x400 through 0xFFF in the PCI-to-PCI bridge address space.
This address range contains IDT proprietary registers that are port specific. Registers in this address range
may be accessed using PCI configuration requests to the corresponding PCI-to-PCI bridge function 0
header, global address space access registers, SMBus, or serial EEPROM. Figure 14.2 shows the organi-
zation of the proprietary port specific registers. Offset addresses for proprietary port specific registers are
listed in Table 14.5. Offset addresses are with respect to the corresponding PCI-to-PCI bridge function 0
base address.
Registers in this address range are referenced as Px_REGNAME where x represents the PES48T12G2
port number and REGNAME represents the register name in Table 14.5. Reading from or writing to an
address not defined in Table 14.5 completes successfully but has an undefined effect.
Figure 14.2 Proprietary Port Specific Register Organization
Physical Layer Registers
Reserved
0x400
0x510
0x560
0xFFF
Global Address Space
Access Registers
0xFF8
Reserved
Request Metering
0x880
0x890
Power Management
Registers
0x700
Internal Error Reporting
Control and Status Registers
Port Control and
Status Registers
0x480