IDT 89HPES48T12G2, User Manual

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IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PES48T12G2 User Manual 15 - 8 April 5, 2013
PMBASEU - Prefetchable Memory Base Upper Register (0x028)
PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)
IOBASEU - I/O Base Upper Register (0x030)
IOLIMITU - I/O Limit Upper Register (0x032)
3:1 Reserved RO 0x0 Reserved field.
15:4 PMLIMIT RW 0x0 Prefetchable Memory Address Limit. The PMBASE, PMBASEU,
PMLIMIT and PMLIMITU registers are used to control the forward-
ing of prefetchable transactions between the primary and second-
ary interfaces of the bridge. This field contains A[31:20] of the
highest memory address, with A[19:0] assumed to be 0xF_FFFF,
that is below the primary interface of the bridge. PMLIMITU speci-
fies the remaining bits
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 PMBASEU RW 0xFFFF_FFFF Prefetchable Memory Address Base Upper. This field specifies
the upper 32-bits of PMBASE when 64-bit addressing is used.
When the PMCAP field in the PMBASE register is cleared, this
field becomes read-only with a value of zero.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 PMLIMITU RW 0x0 Prefetchable Memory Address Limit Upper. This field specifies
the upper 32-bits of PMLIMIT.
When the PMCAP field in the PMBASE register is cleared, this
field becomes read-only with a value of zero.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 IOBASEU RW 0xFFFF I/O Address Base Upper. This field specifies the upper 16-bits of
IOBASE.
When the IOCAP field in the IOBASE register is cleared, this field
becomes read-only with a value of zero.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 IOLIMITU RW 0x0 IO Limit Upper. This field specifies the upper 16-bits of IOLIMIT.
When the IOCAP field in the IOBASE register is cleared, this field
becomes read-only with a value of zero.
Bit
Field
Field
Name
Type
Default
Value
Description