IDT 89HPES48T12G2, User Manual, Page: 140 / 276

IDT SMBus Interfaces
PES48T12G2 User Manual 12 - 8 April 5, 2013
Notes The following I/O expander configuration sequence is issued by PES48T12G2 to I/O expanders 12 and
13 (i.e., the one that contains link up and link activity status).
– Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7)
to I/O expander register 2.
– Write link activity status for all ports to the upper eight I/O expander pins (i.e., I/O-1.0 through I/O-
1.7) to I/O expander register 3.
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select all outputs in the lower eight I/O expander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all outputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
While the I/O expander is enabled, PES48T12G2 maintains the I/O bus expander signals and the
PES48T12G2 internal view of the hot-plug signals in a consistent state. This means that whenever that I/O
bus expander state and the internal view of the signal state differs, an SMBus transaction is initiated to
resolve the state conflict.
– An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs,
one or more hot-plug register control fields may be re-initialized to its default value. When this
occurs, the internal state of the hot-plug signals is in conflict with the state of I/O expander hot-
plug output signals. In such a situation, PES48T12G2 will initiate an SMBus transaction to modify
the state of the I/O expander hot-plug outputs.
PES48T12G2 has one combined I/O expander interrupt input, labeled IOEXPINTN, which is a GPIO
alternate function. Associated with each I/O expander is an open drain interrupt output that is asserted
when an I/O expander input pin changes state. The open drain I/O expander interrupt output of all I/O
expanders should be tied together on the board and connected to the appropriate GPIO. Whenever IOEX-
PINTN is asserted, PES48T12G2 reads the state of all I/O expanders. Since the I/O expander interrupt
input is a GPIO alternate function, the corresponding GPIO should be initialized during configuration to
operate in alternate function mode (for further information, see Chapter 12, General Purpose I/O.)
Whenever PES48T12G2 needs to change the state of an I/O expander signal output, a master SMBus
transaction is initiated to update the state of the I/O expander. This write operation causes the corre-
sponding I/O expander to change the state of its output(s). PES48T12G2 will not update the state of an I/O
expander output more frequently than once every 40 milliseconds. This 40 millisecond time interval is
referred to as the I/O expander update period.
Whenever an input to the I/O expander changes state from the value previously read, the interrupt
output of the I/O expander is asserted. This causes PES48T12G2 to issue a master SMBus transaction to
read the updated state of all I/O expander inputs. Regardless of the state of the interrupt output of an I/O
expander, PES48T12G2 will not issue a master SMBus transaction to read the updated state of the I/O
expander inputs more frequently than once every 40 milliseconds (i.e., the I/O expander update period).
This delay in sampling may be used to eliminate external debounce circuitry.
The I/O expander interrupt request output is negated whenever the input values are read or when the
input pin changes state back to the value previously read. PES48T12G2 ensures that I/O expander trans-
actions are initiated on the master SMBus in a fair manner. This guarantees that all I/O expanders have
equal service latencies. Any errors detected during I/O expander SMBus read or write transactions is
reflected in the status bits of the SMBus Status (SMBUSSTS) register.