IDT 89HPES48T12G2, User Manual

Page: 55 / 276

Notes
PES48T12G2 User Manual 4 - 1 April 5, 2013
®
Chapter 4
Clocking
Introduction
Figure 4.1 provides a logical representation of the PES48T12G2 clocking architecture. The
PES48T12G2 has a single differential global reference clock input (GCLK).
Figure 4.1 Logical Representation of the PES48T12G2 Clocking Architecture
The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and
GCLKN[1:0] pins.
– The nominal frequency of the global reference clock input may be selected by the Global Clock
Frequency Select (GCLKFSEL) pin to be either 100 MHz or 125 MHz.
– Both global reference clock differential inputs should be driven with the same frequency. There
are no skew requirements between the GCLKP[0]/GCLKN[0] and GCLKP[1]/GCLKN[1] inputs.
Any constant phase difference is acceptable.
– The Global Clock supports Spread Spectrum Clocking (SSC).
– The global reference clock input is provided to each SerDes quad and to an on-chip PLL.
• The on-chip PLL uses this clock to generate a 250 MHz core clock that is used by internal switch
logic (e.g., switch core, portion of a stack, etc.).
• The PLL within each SerDes quad generates a 5.0 GHz clock used by the SerDes analog
portion (PMA) and a 250 MHz clock used by the digital portion (PCS).
Port Clocking Mode
Port clocking refers to the clock that a port uses to receive and transmit serial data. All ports in the switch
use the global reference clock (GCLK) input for receiving and transmitting serial data. The switch does not
introduce any requirements on the global reference clock input beyond those imposed by PCI express.
Depending on the system configuration, a port may employ the common Refclk or separate Refclk architec-
tures defined by the PCIe Base specification.
SerDes
Quad
Port 0
Stack
SerDes
Quad
Port 1
Stack
SerDes
Quad
Port 9
Stack
SerDes
Quad
Port 12
Stack
SerDes
Quad
Port 13
Stack
Switch Core
PLL
GCLK
Port 0 Port 1 Port 9 Port 12 Port 13
...