IDT 89HPES48T12G2, User Manual, Page: 17 / 276

Notes
PES48T12G2 User Manual ix April 5, 2013
List of Figures
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Figure 1.1 PES48T12G2 Block Diagram ............................................................................................1-3
Figure 1.2 PES48T12G2 Logic Diagram .............................................................................................1-5
Figure 2.1 Transparent PCIe Switch ...................................................................................................2-2
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers .................................................3-3
Figure 3.2 Architectural Model of Arbitration .......................................................................................3-5
Figure 3.3 PCIe Switch Static Rate Mismatch ....................................................................................3-8
Figure 3.4 PCIe Switch Static Rate Mismatch ....................................................................................3-8
Figure 3.5 Request Metering Count and Initial Value Loaded ............................................................3-9
Figure 3.6 Decrement Value and Decrement Value Adjustment .......................................................3-10
Figure 3.7 Request Metering Counter Decrement Operation ............................................................3-11
Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation ...............................3-11
Figure 4.1 Logical Representation of the PES48T12G2 Clocking Architecture ..................................4-1
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................5-4
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................5-4
Figure 6.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 ..........................................6-2
Figure 6.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 ..........................................6-2
Figure 6.3 Merged Port Lane Reversal for Maximum Link Width of x2 ...............................................6-3
Figure 6.4 Merged Port Lane Reversal for Maximum Link Width of x4 ...............................................6-4
Figure 6.5 Merged Port Lane Reversal for Maximum Link Width of x8 ...............................................6-5
Figure 6.6 PES48T12G2 ASPM Link Sate Transitions .....................................................................6-12
Figure 7.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................7-10
Figure 7.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................7-10
Figure 7.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB
Nominal de-emphasis ......................................................................................................7-11
Figure 8.1 ACS Source Validation Example .......................................................................................8-4
Figure 8.2 ACS Peer-to-Peer Request Re-direct at a Downstream Port ............................................8-4
Figure 8.3 ACS Upstream Forwarding Example .................................................................................8-5
Figure 8.4 Error Checking and Logging on a Received TLP .............................................................8-15
Figure 9.1 Hot-Plug on Switch Downstream Slots Application ............................................................9-1
Figure 9.2 Hot-Plug with Switch on Add-In Card Application ..............................................................9-2
Figure 9.3 Hot-Plug with Carrier Card Application ..............................................................................9-2
Figure 9.4 Power Enable Controlled Reset Output Mode Operation ..................................................9-5
Figure 9.5 Power Good Controlled Reset Output Mode Operation .....................................................9-5
Figure 9.6 PES48T12G2 Hot-Plug Event Signalling ...........................................................................9-7
Figure 10.1 PES48T12G2 Power Management State Transition Diagram .........................................10-2
Figure 12.1 Split SMBus Interface Configuration ................................................................................12-1
Figure 12.2 Single Double Word Initialization Sequence Format ........................................................12-3
Figure 12.3 Sequential Double Word Initialization Sequence Format .................................................12-3
Figure 12.4 Configuration Done Sequence Format ............................................................................12-4
Figure 12.5 Slave SMBus Command Code Format ..........................................................................12-14
Figure 12.6 CSR Register Read or Write CMD Field Format ............................................................12-15
Figure 12.7 Serial EEPROM Read or Write CMD Field Format ........................................................12-17
Figure 12.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled 12-18