IDT 89HPES48T12G2, User Manual

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IDT Link Operation
PES48T12G2 User Manual 6 - 11 April 5, 2013
Notes – The port handles all TLPs that target the port’s function(s) normally.
• It is possible to perform configuration read and write operations to port.
When a link comes up, flow control credits for the configured size of the port’s IFB queues are adver-
tised. A link down condition on a downstream port’s link may cause the Surprise Down Error Status
(SDOENERR) bit to be set in the port’s AER Uncorrectable Error Status (AERUES) register. The conditions
under which surprise down is reported are described in Section 3.2.1 of the PCI Express 2.0 Specification.
In addition to the exception conditions listed in Section 3.2.1of the PCI Express 2.0 specification, the
SDOENERR bit in a port’s AERUES register is not set in the following cases:
– The port’s link is fully retrained via the FLRET bit in the PHYLSTATE0 register.
– The port’s clocking mode is modified (see section Port Clocking Mode on page 4-1).
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by an upstream port, then the fields in the message
are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.
Downstream Port
A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following
events occur.
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream port is up.
– A link associated with the downstream port transitions from a non-operational state to an opera-
tional (i.e., data-link layer up) state.
Link States
PES48T12G2 ports support the following link states:
– L0
Fully operational link state
– L0s
Automatically entered low power state with shortest exit latency
– L1
Lower power state than L0s
May be automatically entered or directed by software by placing the device in the D3
hot
state
– L2/L3 Ready
The L2/L3 state is entered after the acknowledgement of a PME_Turn_Off Message.
There is no TLP or DLLP communications over a link in this state.
Note that in this state, the link is considered ‘up’.
– L3
Link is completely unpowered and off
– Link Down
A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the
LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states.